This SRAM has embedded ECC on chip. The ECC mechanism will detect a single bit error if it is present and will automatically correct the error when a read is performed. So when you are reading say one of the bits is corrupted. The internal ECC will first read the bits detect one bit corruption correct it in the internal buffers and give the data out, but it will not write back the correct data in the memory location. The memory location still has corrupt data. On seeing the ERR pin asserted ( on those chips which have ERR pin) the user will understand that one bit error was detected and corrected for read and then he can write back the same data on to the memory location thereby correcting the error.
You can read more about this in our app note on page 5, 6, 7.
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This device (CY62148G30) has not ERR terminal.
How do we determine if an error occurs?
The device which does not have ERR pin, the user in that case cannot determine if an error has occurred. The errors will keep on accumulating and single bit error can turn into multi bit error but since the time taken will be very long as you can check in the SER reports that it will not affect any applications as SER rate for ECC devices is less than 0.1 FIT/Mb.
Thank you for your response.
This device does not have an "ERR terminal" and "write back function".
From the above two points,
In applications that do not turn off the power for a long time,
Although single bit errors are automatically corrected, errors in the cells themselves can not be improved.
That's because it doesn't have a write back feature.
Because this device does not have an ERR terminal,
Even as an application, it is not corrected that an error has occurred because it is automatically corrected by ECC.
After a long time, a multi-bit error occurs.
I understand that SRAM can not correct data.