2 Replies Latest reply on May 16, 2019 3:00 PM by BushraH_91

    S25FS512 verilog model


      I've found a SPI NOR Cypress S25fs512s Verilog Model (https://www.cypress.com/verilog/s25fs512s-verilog ) and I get confuse: Spec says that

         Read only bits are never modified and the related bits in the WRAR command data byte are ignored without setting a program or erase error indication (P_ERR or E_ERR in SR1V). Hence, the value of these bits in the WRAR data byte do not matter.

      However in the model, I see that:


      SR1_V[7] is SRWD bit, it is a Volatile copy of SRWD_NV and a Read only bit, but in above code, it is always updated with data programed by WRAR command. If there is a mistake here ?