need help on power supply section of psoc-5lp  for best performance of 20bit adc

quad,

I'm not sure what you are specifically referring to regarding "regulated or unregulated".  Can you be more specific?  Are you referring to the Power supply to the PSoC or the ADC vref voltage?

General Principles

The PSoC can operate over a fairly wide-range of supply voltage.  2.0V to 5.5V.  IT IS ALWAYS BETTER TO HAVE A STABLE, RELIABLE POWER SUPPLY VOLTAGE!

If you're using the PSoC5LP-kit, it's normally powered by USB @ 5V nominal.  In reality it is about 4.7V +/- 10%.  It should be fine for all digital circuits but some care needs to be used for analog circuits.

I have found to get the most stable and reliable ADC readings I use the internal reference source  .  I recommend on the 5LP-kit to set the ADC vref to Internal Bypassed to pins P0.3 or P3.2.  These pins have a 1uF cap on it to better stable the vref signal.  By using the internal voltage source, your ADC readings will be virtually immune from Vdd power supply fluctuations.

Since you are using 20bits for the ADC, it is going to be near to impossible to eliminate jitter in the signal.  There is going to be multiple sources of noise such as thermal, radiated emissions and more.  Therefore, if possible, take multiple readings and average the result.

I hope this helps.

Len

quad,

Are you planning on using the 5LP-kit as the base of the design or are you designing a totally new PCB with the PSoC5LP on it?

If you're using the 5LP-kit as the base, then the USB power is all you get unless you remove R20 on the PCBA and supply your own power to J4 pin 2.

Either way, if you supply your own power, REGULATED is ALWAYS BETTER.

You can purchase very low-cost LDO (Low-DropOut) linear regulators that are easy to design.  An LDO is generally better if you're looking for 20-bit performance.  This is because switching power supplies can be prone to emitting radiated EMI that might be seen by the inputs to your ADC design.  This can be a large contributor to the input signal jitter I mentioned earlier.

Len

quad,

Are you happy with the ADC performance on your PSoC5LP-kit prototype?

If so, look at the 5LP-Kit schematics.  This will give to a decent hint how to connect all VDDx, VCCx, VDDIOx, VSSa and VSSd connections along with the bypass cap values.

What is the source of your power supply?  A battery (vehicle or  power cell)?  A wall-AC converter to 5V DC?

Next, you need to consider the susceptibility of your analog inputs to radiated (RE) or conducted (CE) EMI.

Here is a general rule:  Make sure you have a very low-impedance path from your GND-referenced input and VSSA pins on the PSoC.  It is better to use differential input mode to improve RE and CE EMI immunity.  It is preferable to use a 4-layer PCB design especially if there is a lot of routing around the PSoC.   Using a 2-layer PCB requires much more care in the layout to prevent break-up of GND path.

I've looked at the PSoC 5LP TRM.  Are you referring to Section 15.2 Block Diagram, Figure 15-1. Power Domain Block Diagram?

Len

Hi,

the P5LP (and P3) has several voltage domains (see detailed explication in DS - https://www.cypress.com/documentation/datasheets/psoc-5lp-cy8c58lp-family-datasheet-programmable-system-chip-psoc , page 12)

I assume that you are going to make a "simple" PCB using, if possible, only one voltage

I assume that everything about how to deal with high resolution ADC and small signals is observed (trace of PCB, filtering, components used, etc,etc) 

I don't know what's your voltage in your circuit. As Len said, for high resolution ADC is always better to use LDO (no switching), with its filtering / decoupling.

On the side of P5LP, it's better to use those pins with "quasi" direct connection to ADC (internal routing in P5LP is intended to minimize the possible crosstalk noise between analog, digital, clocks, etc See AN58304 and others)

You can use only one voltage for all power supply pins: VDDA (must be the highest), VDDD, VDDIO(0,1,2,3).

PIns VCCA and VCCD are generated, so, you need only decoupling capacitors (see fig 2-5 in DS).

In case you have to connect signals with other voltage levels (i.e. your main power is 5V but you have devices powered at 3.3V and 1.8V), you can connect VDDIOx at the voltage of your device (you can have until 4 different domains) so, you don't need voltage translators. If it's not your case, connect VDDIOx to VDDA

Follow the recommendation if you're not going to use battery (VBAT) and / or you don't need boost the voltage (i.e in the case you are usin solar panel)

A recommendation (my experience): for high resolution, use external Vref (1.024 as max. voltage). I use LM4140 with very good results.

B.R.

Gil

Hi quad,

read AN58304 carefully.. You have the info about what pins (and ports) are better to use for analog.

VCCA and VCCD: it's 1uF. Follow the rules described in DS. (there is also a example of PCB how to distribute the capacitors).

why to use voltage level shifters when you can connect them to P5LP directly? You only need to apply 3.3V to the VDIOxx that cover the port pins used.

Imagine that you have a AND gate (3 inputs), with inputs at 5V level but you need the output connected to 3.3V level. A solution: input: P5[0..2] and VDIO01 = 5V; Output: P6[7] and VDIO02 = 3.3V. Done.

B.R

Gil

quad,

A smps is OK if the smps circuit is not on your PCB.  If it is in a "wall-wart" module with a DC output, the physical distance to your PCB will be most likely enough isolation.  If the smps is very close to your PCB, not so much.

If the smps is a regulated DC output at 12V, then here is a simple low-cost circuit to use to output 5V to the PSoC and downstream circuits.

The Vreg U_1 can be a very low-cost LDO with a fixed 5.0V output.  Note: most SMD LDOs are about 100mA max output.  With proper thermal design, you can use a 1A version (usually a beefier package) if needed.

The bulk caps C_2 and C_3 are for low-frequency mostly load variances.  C_4 (smaller value but high-frequency lower-impedance) is used to filter possible smps-induced high frequency noise from passing through the Vreg.

Len