Problem PSoC 4 SPI DMA

[thwic_4148901]

Hello,

I'm trying to use SPI with DMA on PSoc 4 on the CY8CKIT-044.

I started with the code example SPI Master DMA (https://www.cypress.com/documentation/code-examples/ce224339-psoc-4-spi-master). I removed the receive part because I just need to send an int-array with 1253 elements.

I checked with an oscilloscope if I'm sending data on the MOSI and SCLK and both looks as expected.

For code and configuration please have a look at the attached project.

I have two problems with my project:

1. I want to generate an interrupt after DMA sent all 1253 elements. When the interrupt is triggered, the ISR should set a pin to 1. When I watch this pin with an oscilloscope I can see that there are 2 interrupts shortly after each other. Does somebody have an idea why I get 2 interrupts?
2. Is there a possibilty to get an interrupt after the SPI is done with sending all the 1253 elements? If I turn on the SPI done interrupt source then I get an interrupt after every byte which was sent. I need to set a pin to 1 for about 30ns after the SPI is done.

Thank you very much in advance!

Best regards.

[BragadeeshV · Accepted solution]

hI thomas.wiesnet_4148901​,

From the SPI configurator I see that you have set TX FIFO level to 7. But in the DMA configurator, you have not checked the Increment destination address by four. Can you set TX FIFO level to 1 and leave the increment destination address by four unchecked. This will make the DMA trigger whenever the TX FIFO is empty. But you have to disable the channel as soon as the 1253 elements is transferred so that the DMA is not triggered again until re-enabled. This can be done in the callback function.

Also, since you need to trigger an interrupt every time a descriptor completes, set  no of data elements to transfer as 1253.

You will not be able to generate an SPI interrupt after 1253 interrupt completes along with DMA. You can only generate interrupts that are given in the SPI component datasheet. (ie) DMA implementation requires hardware FIFO.

But if you are not using DMA, then you can set TX buffer size to 1253 , which utilizes a software buffer  and an internal ISR to handle data transfer from buffer to TX FIFO. You can then use the TX FIFO empty interrupt to check if all the bytes are transferred from the TX FIFO

Regards,

Bragadeesh

[thwic_4148901]

Hello BragadeeshV_41​,

thank you very much.

I changed the the TX FIFO level to 1 in the SPI configurator and left the Increment destination address by four unchecked.

Now there is only one interrupt left, because of disabling the channel in the callback function, that worked.

Unfortunately I have to use the combination of SPI and DMA that's why I can't go for the SPI interrupts.

Thank you very much for your help.

Regards,

Thomas

[thwic_4148901]

Hello BragadeeshV_41​,

thank you very much.

I changed the the TX FIFO level to 1 in the SPI configurator and left the Increment destination address by four unchecked.

Now there is only one interrupt left, because of disabling the channel in the callback function, that worked.

Unfortunately I have to use the combination of SPI and DMA that's why I can't go for the SPI interrupts.

Thank you very much for your help.

Regards,

Thomas