// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
// Set Slave FIFO mode
IFCONFIG |= 0x03;
SYNCDELAY;
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
REVCTL = 0x01;//0x01 //Cypress highly recommends setting both bits to 1
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// default: all endpoints have their VALID bit set
// default: TYPE1 = 1 and TYPE0 = 0 --> BULK
// default: EP2 and EP4 DIR bits are 0 (OUT direction)
// default: EP6 and EP8 DIR bits are 1 (IN direction)
// default: EP2, EP4, EP6, and EP8 are double buffered
SYNCDELAY;
PINFLAGSAB = 0xEC;
SYNCDELAY;
PINFLAGSCD = 0x13;
SYNCDELAY;
PORTACFG = 0x40; // func. of PA7 pin is SLCS#
SYNCDELAY;
FIFOPINPOLAR = 0x3F;
//FIFOPINPOLAR = 0x00;
SYNCDELAY;
// we are just using the default values, yes this is not necessary...
EP1OUTCFG = 0xA0;
EP1INCFG = 0xA0;
SYNCDELAY; // see TRM section 15.14
EP2CFG = 0xDA; //ISO
SYNCDELAY;
EP4CFG = 0x00;
SYNCDELAY;
EP6CFG = 0x00; //ISO
SYNCDELAY;
EP8CFG = 0x00;
EP2ISOINPKTS=0x81;
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x04; // reset, FIFO 4
SYNCDELAY; //
FIFORESET = 0x06; // reset, FIFO 6
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY;
EP2FIFOCFG = 0x00;
EP4FIFOCFG = 0x00;
EP6FIFOCFG = 0x00;
EP8FIFOCFG = 0x00;
SYNCDELAY;
EP2FIFOCFG = 0x4D;
//EP6FIFOCFG = 0x4D;
SYNCDELAY;
// out endpoints do not come up armed
// since the defaults are double buffered we must write dummy byte counts twice
/* SYNCDELAY;
EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY;
EP2BCL = 0x80;
SYNCDELAY;
EP2BCL = 0x80;
SYNCDELAY;
EP8BCL = 0x80; // arm EP8OUT by writing byte count w/skip.
SYNCDELAY;
EP8BCL = 0x80; */
// enable dual autopointer feature
AUTOPTRSETUP |= 0x01;
