S25FL512SAGMFI011 programming issue

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
sakoc_3630876
Level 1
Level 1

Hi all,

I'm using S25FL512SAGMFI011 for my bit stream storage with SPI interface operating @ 20MHz. I'm using CM3 to program the device, able to read idcode and status register correctly. so with the checking WEL and WIP bit i'm continuing to program, when ever WIP bit is "0" as stated in datasheet. But when i'm trying to read back using 0x03 it is giving all "0xFF". How can we sure that program is happened or happening other than WIP bit in status register?.

Can you guys please help me with this?

Thanks,

santosh koppaka@

0 Likes
7 Replies
BushraH_91
Moderator
Moderator
Moderator
750 replies posted 50 likes received 250 solutions authored

Hello,

Thank you for contacting Cypress Community Forum. Currently we reviewing the issue and will get back to you as soon as we find the resolution.

Thank you

Regards,

Bushra

0 Likes

Hello,

Unfortunately, we are not familiar with CM3 programmer. But if you have access to the driver code and/or probing flash signals, we can try to debug.

As to the question “How can we sure that program is happened or happening other than WIP bit in status register” – this can be done by checking the WIP transactions, i.e., after sending program command, check SR1, if WIP changes to 1, means the program command is accepted by flash. Keep checking SR1, when WIP goes back to 0 again, and WEL is also cleared to 0, that means program completes successfully. If WIP does not change to 1 after sending program command, i.e., the WIP remains 0 and WEL remains 1. This may indicate the program command is not accepted by flash at all. As WEL is cleared to 0 by any success program/erase operation, so WREN (set WEL to 1) command is required prior to every program/erase command.

Please do following experiments and send us the result so we can have better understanding of the issue:

  1. Test with address space in the lowest 128Mb (16MB)  (higher address space >16MB will need to set banks address register to access the space beyond 24-bit (3-byte) addressing space)
  2. Program a few words
  3. Read the SR1 and record the full SR1 for us to analyze
  4. Read SR1 until both WEL & WIP go to 0
  5. 0x03 read the programmed addresses

If you can’t modify the code to do the suggested test. Then try to capture Logic Analyzer traces at the flash pins while sending program command.

Thank you

Regards,

Bushra

0 Likes

Hi Bushra,

Thanks for your reply, we are following the below sequence for programming flash and we aqre facing the issue. tried with 61 bytes of data as well as big data. Getting "FF". when reading.

Note: we can able to read status and configuration registers correctly. But problem is with when we are reading from memory using 03h command

  1. Check Status Reg,S0: WIP(CMD=05h)
  2. Write Enable(CMD=06h)
  3. Check Status Reg,S1: WEL(CMD=05h)
  4.   Erasing the sector before programming (CMD = 20h)
  5. Check Status Reg,S0: WIP(CMD=05h)
  6. Write Enable(CMD=06h)
  7. Page Program (02h)
  8. Check Status Reg,S0: WIP(CMD=05h)
  9. Read data(CMD=03h).

I can able to see the data while programming on beagle SPI analyser and device giving WIP as 1 during writing and iam waiting up to WIP bit to 0 for sending next page of data.

page size - 512 bytes and 256 bytes tried.

Please reply to my mail-id so that I can forward my code. Here we are using CM1 not CM3.

Thanks,

Santosh koppaka

santosh.koppaka@microchip.com

0 Likes
lock attach
Attachments are accessible only for community members.

Hi,

Please find attached data captured using Beagle SPI protocol analyser. And .c files for your reference. Please reply, missing anything.?

Thanks,

Santosh Koppaka

0 Likes

Hello,

Thank you for sending the information. Currently we are reviewing the issue and will get back to you as soon as we find the resolution.

Have a wonderful day

Regards,

Bushra

0 Likes
lock attach
Attachments are accessible only for community members.

Hello Santosh,

Please see the Beagle logs with comments attached (the text highlighted in green are the suggested debugging code to add).

More suggested test and questions are as below:

  1. Is CS# signal connected to Vcc through a pull-up resister?
  2. Read data (CMD=03h) at a location contains known data. This is to verify if it is read problem, or page program issue
  3. Check signals timing waveform for erase/program/read operation – CS# needs to be pulled high after command + address + input data, the width of CS# low must be multiple of 8 clocks (e.g., 8-bit command code + 24-bit address, then the width of CS# low should be 32 clock cycles).
  4. If step 2 confirmed Read data (CMD=03h) works, then read PPB Access Register and DYB Access Register values for the tested sector.

In the test flow you described

  1.   Erasing the sector before programming (CMD = 20h)

Is it really 20h? 20h is not supported in FL512S. And I see in the beagle logs, the erase command is D8h.

Thank you

Regards,

Bushra

0 Likes

Hello Santosh,

Any update? Is your issue resolved?

Thank you

Regards,

Bushra

0 Likes