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Hi,
is it possible to initialize a register value in PSoC verilog implementation? I tried "reg A = 1'b1;" on register definition, but it isn't accepted. I didn't find anything in the documentation.
Regards
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PSoC 5LP
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Ralf,
In Warp Verilog, all registers are initialized to 0 by default. Also, Warp ignores the 'initial' construct, so no luck there. I see only way is to use a reset condition to initialize values to something non-zero.
/odissey1
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Ralf,
In Warp Verilog, all registers are initialized to 0 by default. Also, Warp ignores the 'initial' construct, so no luck there. I see only way is to use a reset condition to initialize values to something non-zero.
/odissey1
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Hello odissey & Ekta,
thank you for confirmation, I thought I've overseen it.
Regards
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Hello
You can assign register some value only inside 'always' block. You can refer to the section 2.3.2 (Register) of the Warp_verilog_reference book (page 10): https://www.cypress.com/file/326096/download . Without assigning any value the registers are initialized to zero.
In the above example, in order to assign value 3 to register count, reset variable has been used inside an 'always' block
Regards
Ekta