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Hi,
I added the "Emulated EEPROM" component into my PSoC6 design and after this the build consistently fails with:
App.elf: Merge error: Section 0x14000000 at App.elf overlaps section 0x14000000 from App_signed.elf, but it contains different data
The command 'C:\Program Files (x86)\Cypress\PDL\3.0.1\tools\win\elf\cymcuelftool.exe' failed with exit code '1'.
Looking in the .map file that was generated around 0x14000000 shows this:
cy_em_eeprom 0x14000000 0x1400
*(.cy_em_eeprom)
.cy_em_eeprom 0x14000000 0x10bd .\CortexM4\ARM_GCC_541\Debug\BLE_config.o
*fill* 0x140010bd 0x143
.cy_em_eeprom 0x14001200 0x200 .\CortexM4\ARM_GCC_541\Debug\Em_EEPROM_1.o
0x14001200 Em_EEPROM_1_em_EepromStorage
Before it was merely:
.cy_em_eeprom 0x14000000 0x10bd
*(.cy_em_eeprom)
.cy_em_eeprom 0x14000000 0x10bd .\CortexM4\ARM_GCC_541\Debug\BLE_config.o
Disabling the EEPROM component reverst the .map file change and build succeeds as before.
Further looking into the App.elf and App_signed.elf files:
App.elf:
Contents of section .cy_em_eeprom:
14000000 00000000 00000000 00000000 00000000 ................
...
140010b0 00000000 00000000 00000004 11 .............
App_signed.elf:
Contents of section .cy_em_eeprom:
14000000 00000000 00000000 00000000 00000000 ................
...
140010b0 00000000 00000000 00000004 11000000 ................
...
140013f0 00000000 00000000 00000000 00000000 ................
Clearly the signed ELF file has the emulated EEPROM data but the regular ELF does not.
Looking into it further, it seems that the ELF file for the M0 core only has the EEPROM data in the .cy_em_eeprom section but the M4 has both the BLE and EEPROM data and merging these two together is causing the problem.
I also created a fresh project with only these two components and got the same error.
Is there a correct way to fix this problem?
- Juha
Solved! Go to Solution.
- Tags:
- emulated eeprom
- psoc6
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Since you have the BLE and the EEPROM component present which place data in the working flash, the memory regions need to aligned accordingly. Please refer to this thread for the solution, it is based on the same error: EEPROM compile error
Regards,
Dheeraj
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Hello Juha,
I have been trying to recreate your issue but have been unsuccessful. Can you please share your project? If not please explain the steps in detail to reproduce the issue.
Regards,
Dheeraj
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Hello Dheeraj,
My repro steps were simply:
1. Create a new empty project for the CY8C6347BZI-BLD53
2. Add BLE and Em_EEPROM components to the top design, with default settings.
3. Build
No changes to any files besides the top design were made.
I have also attached a project that demonstrates the problem.
I seem to be using PDL 3.0.1 version of the cymcuelftool.exe and both BLE and EEPROM component are at 2.0. Quick trial to update the components to 2.1 and 2.2 respectively did not change the behavior.
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PDL 3.0.3 cymcuelftool fails the same way.
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Since you have the BLE and the EEPROM component present which place data in the working flash, the memory regions need to aligned accordingly. Please refer to this thread for the solution, it is based on the same error: EEPROM compile error
Regards,
Dheeraj
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Hi Dheeraj,
Thank you for the suggestions. Can you elaborate on what the BLE component uses the EEPROM space for? Will there be any downside to having the same data stored twice? Can it change so that they are not in sync anymore? Further, if the dual-core BLE mode is used (CM0+ and CM4) which core needs access to that data?
Thanks,
- Juha
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The BLE Component uses the working flash for storing the Bonding List. So if you have an EEPROM component, then you need to be align the memories accordingly.
There is no downside to storing data as long as it doesn't overflow from the region allocated to it. You need to keep the memory regions in sync between the cores. In dual core BLE mode, you allocate region where the BLE host lies.
Regards,
Dheeraj