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Hello ,
I am currently trying to integrate the HyperRam memory and noticed that the signal level from the device is low (less than 1 V).
The picture below shows an example of the waveform coming out of the device when a read access transfer is initiated to the device.
Can you let us know if this level is expected or what could be the electrical issue that will result in such behavior.
The Part number of the device that is being tested is as follows;
- 7KS0641DPHI02
- 810BB341 A
- THAILAND
- Spansion
Thanks and best regards,
Joseph A
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Hi,
Is it possible for you to share schematic diagram of your application with us?
Are the output lines of HyperRAM connected to more than 1 devices?
Thank and Regards,
Sudheesh
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Hello Sudheesh,
We only have one device connected to the memory. See a cut and paste of the schematic for reference.
Regards,
Joseph A
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Hi Joseph,
Did you configure output drive strength of HyperRAM according to your PCB? Output drive strength of HyperRAM can be adjusted by changing the bits 12, 13 and 14 of configuration register 0 (CR0[14:12]). Please refer below sections in datasheet for more information.
- 5.2.1 Configuration Register 0 (page 21)
- 5.2.1.5 Drive Strength (page 24)
Datasheet: https://www.cypress.com/file/183506/download
Thanks and Regards,
Sudheesh
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Hello Sudheesh,
I would like to revisit this topic. I changed the driver circuit in our design and I am still unable to get the HyperRam to respond to read or write transfer requests.
Please use the attached scope waveform as reference. The first shows a memory read access window whilst the second shows a write access transaction. In both cases the HyperRam RWDS pin does not provide a strobe pulses after the designated latency period. The programmed delay is set to 3 cycles.
Can you provide some insight as to what might be wrong.
Thanks and best regards,
Joseph A
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Hi Joseph,
I apologize for the delay in getting back to you.
Are you still facing this issue even after changing the driver strength of HyperRAM device?
Are you meeting the spec tRWR (Read Write Recovery) in your application? The master interface must start driving CS# LOW only at a time when the CA1 transfer will complete after tRWR is satisfied.
Thanks and Regards,
Sudheesh