Register map PDF for CYW20736

[phla_4055536]

Hello,

I downloaded all possible documentation and tooling i could find related to the CYW20736 chip, but i wasn't able to find the register/memory map for memory mapped I/O and memory. I've been able to find a blog post discussing very high level memory layout, but not the per register level memory map. Could someone point me to the right documentation?

Thank you

[MichaelF_56 · Accepted solution]

We do not provide a register map for this device as this level of complexity has been abstracted through the WICED Smart SDK.