5 Replies Latest reply on Mar 21, 2019 10:49 PM by xiaowei.li_3787351

    For S25FL128S, a question about SCK clock.

    xiaowei.li_3787351

      Hi

      I am using the flash chip of CYPRESS,S25FL128SAGNFI000, there is a question that I do not really understand.

       

      Would you help me to solve it?

       

       

      Here is the question:

       

      In this design, the system clock is 200MHz, and the SCK is 100M max.

       

      Does the SCK must be a constant clock for the flash chip?

      Will it be OK as the red line in this picture?  (the SCK stays for a long time of  '0' between the rising edge?)

       

      5.PNG

       

      Please help me...

       

      Thank you very much!

        • 1. Re: For S25FL128S, a question about SCK clock.
          SudheeshK_26

          Hi,

           

          You cannot keep SCK at 0 for a longer time during SPI operations. Please see the clock duty cycles requirements in the below table (https://www.cypress.com/file/448601/download , page 31).

          Thanks and Regards,

          Sudheesh

          • 2. Re: For S25FL128S, a question about SCK clock.
            xiaowei.li_3787351

            Hi,

             

            Thank you for your reply!

             

            Here are my thoughts about this question.

            1, the tWH and tCH are decided by FSCK, and FSCK is the frequency of single commands, the signle commands are shown in the Table 45, which are the Instruction Value  of the commands, such as 05Hex , 07Hex.etc.

             

            But for my situation, the FSCK for the commands are constant, the only difference is that after the command sent to the chip, and then the return data comes out, I need a clock of delay of the SCK...

             

            According to the 3.1.1, it says that "the output data is always available from the falling edge of the SCK clock signal. "

            So I think it will be still OK though there is a clock of delay of SCK...

             

            Are my thoughs available?

            1.PNG

            2.PNG

             

            2, About the SCK, I have a question.

            The tWH and tCH are related to the PSCK, and the PSCK is related to the FSCK.

            Here is the question:

            Because the FSCK can be 50MHz or 100MHz or even 133MHz, (for the single commands),

            what if the FSCK changed in the process of the command, will the commands be working wrong?

             

            Above are my questions, Please help me..

             

            Thank you very much and I am looking forward to your reply~~

            • 3. Re: For S25FL128S, a question about SCK clock.
              SudheeshK_26

              Hi,

               

              Please find our comments below.

              The SPI clock should not change that frequently. You must keep it unchanged for a certain operation (command+address+data -> CS# low cycle (Full transaction)). And of course, you can use 50MHz or lower with single commands, it doesnt have to be 133MHz.

               

              Thanks and Regards,

              Sudheesh

              • 4. Re: For S25FL128S, a question about SCK clock.
                SudheeshK_26

                Hi,

                 

                There were some confusion in my previous responses. You should keep the SPI clock frequency constant while sending a byte of data and it is OK to have delay in SCK signal in between sending different bytes.

                 

                Example: Let us consider a single byte program operation. It consists of PROGRAM command ADDRESS and DATA IN.

                1. It is OK to have a delay in SCK signal after sending the first byte (Command)

                2. It is OK to have a delay in SCK signal between sending first bytes of address and second byte of address etc...

                3. But, it is recommended to have constant SCK frequency while sending Command byte (8 clock cycles), first byte of address (8 clock cycles), second byte of address (8 clock cycles) etc and while programming Data byte (8 clock cycles).

                 

                Please see the waveform attached for a single byte program operation. Programming data 0xA5 to location 0 (3 byte addressing).

                Program Operation.PNG

                Thanks and Regards,

                Sudheesh

                • 5. Re: For S25FL128S, a question about SCK clock.
                  xiaowei.li_3787351

                  Hi ,

                   

                  Thank you so much for your careful reply!

                   

                  I think I have understood this question.

                   

                  And I will design my control codes according to your example!

                   

                  Thank you again and it really helps a lot!!