Using CY22800 for Audio Clock Generation - Lock Time

[CoreyW_81]

We are currently looking for something to generate an MCLK off of an audio bit clock (ranging from 512 kHz to 3.072 MHz).  This would need to be fixed multiplier of either 4x or 8x.  After a  quick look at the CY22800 datasheet, it looks like CY22800-003A or CY22800-006A would be candidate pre-programmed configurations.

Question: How long do these parts take to re-lock on to a new bit clock (for example, when we regain bit clock after losing it, or change sample rates).

[PradiptaB_11 · Accepted solution]

Hi Corey,

The maximum PLL locking time is 3ms. So within 3ms you will see the changes you make onto the configuration.

Thanks,

Pradipta.