1 2 Previous Next 22 Replies Latest reply on Mar 7, 2019 9:10 PM by HemanthR_06 Go to original post
      • 15. Re: EZ-USB FX3 Read FIFO latency
        JaLo_3720291

        Hi Hemanth,

         

        I was testing on the data thought-put. The test environment is in Windows 10. The test procedures are:

        1. The PC keeps bulk out data to the FX3_1 (Slave)

        2. The FPGA* (Master) keeps reading data from the FX3_1.

        3. The FPGA will then write the data to another FX3_2 (Slave).

        4. The PC will continuously bulk in data from FX3_2.

         

        * For step 2, the FPGA actually uses logical 'AND' the DMA ready flag (Empty) and DMA watermark flag (Almost Empty). Therefore, the FPGA can use DMA watermark flag as trigger to terminate the data read. Also, the DMA ready flag can be used as trigger to begin the data read.

         

        * For step 3, the FPGA will check if the DMA ready flag (Full) to see if it can start data write operation. And, check the DMA watermark flag to terminate the current write operation.

         

        I found the following issues:

         

        1. PC makes 16 URB (with timeout=0) to send data to FX3_1. Somehow, the FPGA stopped reading the FX3_1 and PC also no bulk out randomly. Then I check the DMA ready flag and DMA watermark flag of the FX3_1. The DMA ready flag stayed 'HIGH' (active low) and the DMA watermark flag stayed 'LOW' (active low). As, the FPGA logically ANDed both signals. Therefore, the FPGA read stopped.

         

        My question is what makes this issue happen? Does it relate to the watermark flag? I suspect that the DMA still has 1 data word left in the DMA buffer cause the flags not correct. And somehow cause the FPGA think that it read all data out.

         

        Both GPIF interface runs 50MHz. DMA buffer counts is 16. DMA buffer size is 1KB. DMA watermark is 3.

         

        FX3_1:

        watermark: 3

         

        FX3_2:

        watermark: 3

         

        Thanks,

        Jason

         

        • 16. Re: EZ-USB FX3 Read FIFO latency
          HemanthR_06

          Hi Jason,

           

          if you make logical AND of the DMA Ready(active low) and watermark(active low), then FPGA will stop reading after the watermark is low. You also have mentioned the same in your comment.

          But after the watermark flag is asserted, as you already know, there has to be few reads from FPGA(which depends on your watermark setting) that needs to be made before the buffer is emptied. How is this being taken care?

           

          Regards,

          Hemanth

          • 17. Re: EZ-USB FX3 Read FIFO latency
            JaLo_3720291

            Hi Hemanth,

             

            After logical AND of both flags, the FPGA will read 3 more cycles after the ANDed signal asserted and ended the data read by de-asserting the SLRD (de-assert the SLCS and SLOE after 2 clocks). Normally, I can see the DMA ready asserted after the SLCS and SLOE deassert. Therefore, the FPGA will stop reading the FX3. However, when the abnormal case happens, the DMA ready held HIGH (deassert) after SLCS and SLOE de-asserted.

             

            1. Overview of data read

            1.png

            2. Start of data read

            start.png

            3. End of data read

            end.png

            Thanks,

            Jason

            • 18. Re: EZ-USB FX3 Read FIFO latency
              HemanthR_06

              Hi Jason,

               

              - In the Figure 3, related to end of data, I see that neither the DMA RDY Flag nor the DMA water mark flag is asserted. Can you comment on this?

              - Regarding the issue you have told, does it happen sometimes? (What is the frequency?) Normally, instead of 16 URBs, of you just send one DMA buffer worth of data from PC to FX3_1, then can FPGA read that buffer correctly?

               

               

              Regards,

              Hemanth

              • 19. Re: EZ-USB FX3 Read FIFO latency
                JaLo_3720291

                Hi Hemanth,

                 

                - In the Figure 3, related to end of data, I see that neither the DMA RDY Flag nor the DMA water mark flag is asserted. Can you comment on this?

                 

                You can refer to figure 1 for the assert of DMA ready and watermark flags.

                 

                - Regarding the issue you have told, does it happen sometimes? (What is the frequency?)

                 

                It always happens under the following test environment / condition:

                 

                2 python programs are used for this test. Both python programs use libusb1 · PyPI, and I use "zadig-2.4-1.exe" to replace the cypress driver with WinUSB (v6.1.7600.16385).

                 

                Program A:

                Use 16 URBs to transfer 100MB data with timeout = 0

                 

                Program B:

                Use 16 URBs to bulk in data continuously with timeout = 0

                 

                The issue must be happened but not always stop at particular transfer size. I mean it could be stopped at the very beginning of the transfer (like few ten KB), in the middle (a few ten MB) or almost complete (like 9x MB). Because of this random stop, I cannot capture by the logic analyzer. I just know the final pin state and the DMA ready is HIGH and DMA watermark is LOW.

                 

                - Normally, instead of 16 URBs, of you just send one DMA buffer worth of data from PC to FX3_1, then can FPGA read that buffer correctly?

                 

                 

                If I set both # of URB to 1 on both program, I cannot reproduce / see this issue.

                 

                Another findings are:

                1. Keep # of URBs = 16 on both python program and set timeout to a value but not 0. then I cannot see the issue.

                2. Or, I keep # of URBs = 16 and timeout = 0, but stop the FPGA loopback mode, the FPGA just keep receiving data from FX3_1 and then discard them (data sink). Also, the FPGA keep writing data to FX3_2 (data source)  once FX3_2 is not FULL. The issue cannot be observed as well.

                 

                Therefore, I wonder if this issue is related to DMA fail to handle too many URDs then causing the DMA flag operates in abnormal behavior.

                 

                Or, can you advise any API can be called to discard those unread DMA buffer(s) once this issue happens?

                 

                Updates:

                 

                I captured the USB traffic. When this issue happens, the USB stopped transfer due to no ERDY return from FX3. May I ask if the host will stop the outstanding URD(s) unless it receives the ERDY from FX3?

                200MB_URB4_Failed.png

                 

                 

                Thanks,

                Jason

                • 20. Re: EZ-USB FX3 Read FIFO latency
                  HemanthR_06

                  Hi Jason,

                   

                  Having more URBs may not cause DMA Flag abnormal behavior.

                  When the issue occurs can you verify whether the FPGA issued the correct number of reads after water mark is asserted. And also you can check when the issue occurred howmuch of the data FPGA has actually read out from FX3 buffer.

                   

                  Regards,

                  Hemanth

                  • 21. Re: EZ-USB FX3 Read FIFO latency
                    JaLo_3720291

                    Hi Hemanth,

                     

                    We eventually figured out there is a bug in FPGA. We're fixing this bug and will test again. By the way, I have another question:

                     

                    I declared a INTR endpoint which uses to report pin status to the host. Now, I created a DMA channel like below:

                     

                        /* Create a DMA MANUAL_OUT channel for the consumer socket. */

                        /* Set the buffer size based on constants defined in the header file. */

                        dmaCfg.size  = 8;

                        dmaCfg.count = 1;

                        dmaCfg.prodSckId = CY_U3P_CPU_SOCKET_PROD;

                        dmaCfg.consSckId = CY_FX_EP_INTR_CONSUMER_SOCKET;

                        dmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE;

                        dmaCfg.notification = CY_U3P_DMA_CB_CONS_EVENT;

                        dmaCfg.cb = CyFxMainAppDmaCallback;

                        dmaCfg.prodHeader = 0;

                        dmaCfg.prodFooter = 0;

                        dmaCfg.consHeader = 0;

                        dmaCfg.prodAvailCount = 0;

                     

                        status = CyU3PDmaChannelCreate (&glDmaHandle_IntrEp, CY_U3P_DMA_TYPE_MANUAL_OUT, &dmaCfg);

                        if (status != CY_U3P_SUCCESS)

                        {

                            CyU3PDebugPrint (4, "CyU3PDmaChannelCreate failed, Error code = %d\r\n", status);

                            CyFxAppErrorHandler(status);

                        }

                     

                    But I found that I can only commit a buffer unless the host read the content. This behavior causes the host cannot get the latest pin status but the previous one. Can I flush the occupied buffer or modify the content of the buffer and commit again??

                     

                    Thanks,

                    Jason

                    • 22. Re: EZ-USB FX3 Read FIFO latency
                      HemanthR_06

                      Hi Jason,

                       

                      Note that your dmaCfg.size should always be a multiple of 16 bytes.

                      1. For your problem, you can try increasing the dma buffer count. OR

                       

                      You can try doing the following to flush before next commit as you asked:

                      ------------------------

                      CyU3PUsbSetEpNak (EP_NUMBER, CyTrue);

                      CyU3PUsbFlushEp(EP_NUMBER);

                      CyU3PUsbSetEpNak (EP_NUMBER, CyFalse);

                      ------------------------

                       

                      The above way is not tested. So you need to validate it. Check whether you are able to commit after doing the flush.

                       

                      Regards,

                      Hemanth

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