Possible to use PSoC 5 SAR ADC Ratiometrically?

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jopa_1244706
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Considering a CY8C5888AXI-LP096.

I need to measure the ratio of two input voltages at 1 MHz (so using the 12-bit SAR ADCs).  The larger voltage varies from 5V to ~100 mV over a period of perhaps a few ms, while the smaller voltage could be anywhere between 0-100% of the larger one.  I don't care about the values of each signal, just the ratio of the two.

Trying to measure each signal directly against a fixed voltage reference and dividing in software would give poor resolution at the low end of the small signal.  Would it be possible to use the larger voltage as a reference into the SAR ADC so I can take the measurement ratiometrically? 

I'm worried that the reference might be changing too quickly which would not be desirable for the SAR conversion, but I don't know what the limits might be and was wondering if there might be any information regarding the required stability of the SAR ADC reference on this PSOC?  Does this idea seem worth pursuing in general?

Thanks in advance!

John

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John,

I tested PSoC5LP's ADC_SAR for ratiometric approach by setting Vref to a VDAC (Fig A). It worked OK for static (slow) Vref settings with ADC average output value ~2050 (half scale) down to about 140mV (both w/ or w/o Opamp_1 buffer). Below that value, ADC output steadily increases. While sounds promising, unfortunately, PSoC IDE won't let connection of the ADC_SAR to an external input (Fig B), which answers to your question (negatively).

/odissey1

ADC_SAR_Vref_01a.png

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odissey1
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John,

Stable voltage reference is important for SAR_ADC. Please read SAR_ADC operation principles here:

SAR ADCs - Texas Instruments

Since voltage 1 varies quite fast in 50x range, it is not suitable for reference. I see other solutions.

(1) can use an analog division using e.g. AD539 etc. Analog Multipliers & Dividers | Analog Devices

(2) can use two external ADCs with better specs (16-32-bit).

(3) can use oversampling technique to increase S/N in expence of time resolution. See e.g. this

https://www.cypress.com/comment/377701

/odissey1

John,

I tested PSoC5LP's ADC_SAR for ratiometric approach by setting Vref to a VDAC (Fig A). It worked OK for static (slow) Vref settings with ADC average output value ~2050 (half scale) down to about 140mV (both w/ or w/o Opamp_1 buffer). Below that value, ADC output steadily increases. While sounds promising, unfortunately, PSoC IDE won't let connection of the ADC_SAR to an external input (Fig B), which answers to your question (negatively).

/odissey1

ADC_SAR_Vref_01a.png

Thank you so much.  It looks like the answer is to add external circuitry to the PSoC (whether a divider circuit, 16-bit ADC, or both).  The hardware dithering approach looks interesting too--I had already implemented something similar in the software using a moving average but it's good to know of this method as well.

From your experiment it seems that even if I could route the external voltage to the reference terminal, there would still be an issue on the low end of the range (below 140 mV).  So I think I have my answer, thanks again!

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Though... I think you could connect the external VRef using the "external" setting and using the designated pin for that ADC, no?

ExternalVRef.png

Anyway, it does sound like maybe there's a minimum voltage that can be used for the Vref (though I didn't see it mentioned in the specs anywhere).

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John,

I didn't test that. But If this works, it is worth trying. The errors at low end of V1 were small and can be corrected using second ADC for measuring V1 against internal Vref. This is interesting, but off-spec operation for ADC_SAR.

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John,

Attached is result of the static (slow) test. VDAC8 scale is 1.02V. Not bad! Not tested for high speed.

ADC_SAR_Vref_01c.pngADC_SAR_Vref_01b.png

This is very encouraging--there is a measurable signal all the way down to a negligible reference voltage.  The error that shows up at low voltages seems like it could just be an issue of a voltage offset error on the ADC--a self-calibration routine could perhaps alleviate much of that.

"High Speed" is a good point--I'll have to test it in my application.  The reference would be varying in my opinion slowly relative to the 1 MHz sample rate (during which time the conversion takes place), but it's unclear if there's any sort of RC filter on the reference input that might impact the settling time (such a filter would probably be desirable in most applications to reduce noise on the reference).  Only one way to find out I suppose...

Thank you so much for all of your help!

-John

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