Porting from CYPD2122-24LQXIT to CYPD2122-20FNXI

[aldr_3203566]

I am currently working on a project involving a CCG2 CYPD2122-20FNXI chip.

Other topics related to this are as follows…

Design confirmation for CCG2 CYPD2122-20FNXIT charge through USBC to USB2 adapter dongle

https://community.cypress.com/thread/36775

Programming CYPD2122-20FNXI with PSoC creator 3.3 unsupported trouble

https://community.cypress.com/thread/35051

Details on the specifics of the project are below.

I have taken the sample project (due to simplicity of removal of DP and related logic).

Simple CCG2 example firmware for power bank

https://community.cypress.com/community/usb/ez-pd-type-c-usb/blog/2018/03/20/simple-ccg2-example-fir...

This sample is very close to the final goal.

I have changed the device to the CYPD2122-20FNXI, and ported it to the PSoC Creator 4.2 development environment.

The project builds without error, and runs on the CYPD2122-20FNXI (programmed with PSoC MiniProg3), but with some issues… I will outline here.

I also have programmed the CCG2 CY4521 Evaluation Kit (includes CYPD2122-24LQXIT) with this sample project and works as intended, but porting to the CYPD2122-20FNXI results in some issues.

The FET circuit matches the CY4521 Evaluation Kit so logic can be used as-is.

Some differences, VCONN1, VCONN2 are not connected in the CYPD2122-20FNXI design.

+ While the CYPD2122-24LQXIT initially sets up as a DFP (charges the smart phone) when connected to a Samsung Galaxy S8, the CYPD2122-20FNXI sets up as a UFD. How can I setup the the CYPD2122-20FNXI to initially attempt to be a DFP (source)?

+ Attempting to issue a PD role swap via handle_pd_command(DPM_CMD_PR_SWAP, NULL, NULL); results in the PR swap taking place, accepted message, but FETs are not switched correctly… VBUS_MONITOR issue?

+ Running the project in Debug mode, disabling boot loader has issues of the CCG2 failing to respond to a VDM:DiscIdentity request from the accessory, this the accessory appears to drop the communication after repeated attempts. Failure to access data stored in .configSection perhaps?

+ I have been trying to use EZ-PD configuration software for generating the PDO table, it appears support is not available for the CYPD2122-20FNXI, I have been using the PSD table generated for the CYPD2122-24LQXIT as a result.

I have spent the last several days trying to locate these issues without much success.

The most confusing thing is what works on the CYPD2122-24LQXIT does not work on the CYPD2122-20FNXI even though the logic is identical, with exception of VCONN missing, and pins mapped differently.

Current project code and schematic are uploaded.  Any insights on this would be greatly appreciated!

Below is a brief description of the current project and end goal.

The functionality that I am aiming for is a DRP accessory.  This accessory is attached to a USBC based smart phone for USB2.0 data and power delivery.  The power delivery can go either direction, to charge the phone from the accessory, or provide power to the accessory.

The accessory contains a battery and can be mains powered.  While charging could be accomplished through the USBC connection on the accessory, this case may be rare.

The choice of the CYPD2122-20FNXI chip is due to limited space requirements and DRP functionality.  A CCG3 would be more appropriate, but due to space constraints the CCG2 was chosen.

A simple schematic is uploaded, this shows connections to the CCG2.  Consumer and provider control FETs are located on a separate PCB, but are marked on CCG2 pins on the schematic.

[ShifangZ_26 · Accepted solution]

Hi Allan,

1. Kindly refer my comments as below

+ While the CYPD2122-24LQXIT initially sets up as a DFP (charges the smart phone) when connected to a Samsung Galaxy S8, the CYPD2122-20FNXI sets up as a UFD. How can I setup the the CYPD2122-20FNXI to initially attempt to be a DFP (source)?

>> You can change DRP prefered role to SOURCE. But the CCG2 is still toggle Rp/Rd to present it as DRP at the beginning. If you are assured that your design always have power, you can stop to toggle (change Yes yo No). The CCG2 will only present Rp on CC line when CCG2 is not dead battery case.

+ Attempting to issue a PD role swap via handle_pd_command(DPM_CMD_PR_SWAP, NULL, NULL); results in the PR swap taking place, accepted message, but FETs are not switched correctly… VBUS_MONITOR issue?

>> Your VBUS_MON is not correct. By default, CCG2 use P1[6] as VBUS monitor. You just changed the part number with creator but forgot to change the pin assignment as per your hardware. Your case is P2[1].

@psource.c

+ Running the project in Debug mode, disabling boot loader has issues of the CCG2 failing to respond to a VDM:DiscIdentity request from the accessory, this the accessory appears to drop the communication after repeated attempts. Failure to access data stored in .configSection perhaps?

>> I think you can fix the VBUS_MON first and try again.

+ I have been trying to use EZ-PD configuration software for generating the PDO table, it appears support is not available for the CYPD2122-20FNXI, I have been using the PSD table generated for the CYPD2122-24LQXIT as a result.

>> No problem.

Best Regards,

Lisa

[aldr_3203566]

Hi Lisa,

Thank you for your reply!

+ While the CYPD2122-24LQXIT initially sets up as a DFP (charges the smart phone) when connected to a Samsung Galaxy S8, the CYPD2122-20FNXI sets up as a UFD. How can I setup the the CYPD2122-20FNXI to initially attempt to be a DFP (source)?

>> You can change DRP prefered role to SOURCE. But the CCG2 is still toggle Rp/Rd to present it as DRP at the beginning. If you are assured that your design always have power, you can stop to toggle (change Yes yo No). The CCG2 will only present Rp on CC line when CCG2 is not dead battery case.

>> >> Yes, I can confirm I can change with these options.

>> >> I will confirm more with changes to these later when other issues have been resolved.

+ Attempting to issue a PD role swap via handle_pd_command(DPM_CMD_PR_SWAP, NULL, NULL); results in the PR swap taking place, accepted message, but FETs are not switched correctly… VBUS_MONITOR issue?

>> Your VBUS_MON is not correct. By default, CCG2 use P1[6] as VBUS monitor. You just changed the part number with creator but forgot to change the pin assignment as per your hardware. Your case is P2[1].

@psource.c

>> >> Yes, you are correct, I did not notice the definition in the pr_source.h file, this was corrected and behavior between the two platforms is now identical, thank you!

+ Running the project in Debug mode, disabling boot loader has issues of the CCG2 failing to respond to a VDM:DiscIdentity request from the accessory, this the accessory appears to drop the communication after repeated attempts. Failure to access data stored in .configSection perhaps?

>> I think you can fix the VBUS_MON first and try again.

>> >> I still have trouble running in Debug mode, but I think it is the lack of the bootloadable code that isn't running that is the issue.

+ I have been trying to use EZ-PD configuration software for generating the PDO table, it appears support is not available for the CYPD2122-20FNXI, I have been using the PSD table generated for the CYPD2122-24LQXIT as a result.

>> No problem.

>> >> Good to know, thank you!