- Please let us know how you are implementing multiple SPI transfers back to back. Are you pulling the slave select HIGH after every 32 bit transaction? Are the status check and write enable commands issued after every 32 bit transaction? Please share the firmware code snippet if possible.
- Using DMA will reduce the delay since it does not involve the CPU in the transfer path.
EDIT: In case of register mode SPI transfers, the firmware needs to initiate the transfer every time which can cause delays. If your application requires transfer of large number of bytes of data, please use the SPI DMA mode.