Programming FPGA with both devices ON

[agba_3844561]

In order to follow AN84868 instructions and use FPGA Configuration Utility to program the FPGA it is necessary first to power on the FX3 before powering on the FPGA.

Using my own code, I have seen that the PID changes if the FPGA was powered on before the FX3 device. So I tried to configure it nevertheless with that PID and with my own program. I do succeed on programming the FPGA but then I cannot send the bulk transfers. I think the FX3 never turns into slave fifo mode.

I do send it the B1 command, as I said, if I use my code with the FX3 device it works great when powering first the FX3.

The strangest thing is also that I printed UART messages in the following code snipet from cyfxslfifosync::CyFxSlFifoApplnUSBSetupCB():

Header 1

if (bRequest == VND_CMD_SLAVESER_CFGSTAT) {     CyU3PDebugPrint (4, "\r\tVND_CMD_SLAVESER_CFGSTAT\r\n", bRequest);     if ((bReqType & 0x80) == 0x80) {     glEp0Buffer [0]= glConfigDone;     CyU3PUsbSendEP0Data (wLength, glEp0Buffer);     /* Switch to slaveFIFO interface when FPGA is configured successfully*/     if (glConfigDone) {     CyU3PDebugPrint (4, "\r\tSwitch to slaveFIFO interface.\r\n");     CyU3PEventSet(&glFxConfigFpgaAppEvent, CY_FX_CONFIGFPGAAPP_SW_TO_SLFIFO_EVENT, CYU3P_EVENT_OR);     }     isHandled = CyTrue;     } }

As I understand, this is the part that is called when recieving the B1 command in order to change to slave FIFO mode. As the documentation says:

"The FPGA Configuration Utility sends the vendor command 0xB1 (VND_CMD_SLAVESER_CFGSTAT) automatically after all the configuration data has been sent to FX3."

However, this messages ("\r\tVND_CMD_SLAVESER_CFGSTAT\r\n" and "\r\tSwitch to slaveFIFO interface.\r\n") are only printed with the case that is not working!

When it works this messages are not printed.

Some questions:

1. Why does the PID changes if the FPGA was already powered on when I connect the FX3?
2. Is it possible to fix this issue and make the programming work? I have a board that will have FX3 device integrated and both the FPGA and FX3 will be powered at the same time so I don't want to risk it not working.

Thank you.

[SrinathS_16 · Accepted solution]

Hello,

1. The reason for powering up the FX3 first and FPGA later is that the FPGA may drive the PMODE[2:0] pins of FX3. If the desired boot mode is different from the one determined by the FPGA driven PMODE[2:0] lines, FX3 may enumerate improperly. This can lead to different PID being displayed.

2. The UART debug print from the below statement should be printed in both the working and non-working conditions.

CyU3PDebugPrint (4, "\r\tVND_CMD_SLAVESER_CFGSTAT\r\n", bRequest);

Kindly, re-check this. Also, you can use the data read by this vendor command (0xB1). The below statement commits the data to the USB which can be read on the host. Please check and let us know what this value is in both the conditions.

CyU3PUsbSendEP0Data (wLength, glEp0Buffer);

3. Since, you have mentioned that in your design, FX3 and FPGA are powered at the same time, you can ensure that the PMODE[2:0] pins driven by FPGA are the same irrespective of whether FPGA is powered first or FX3 is powered first. It would even be better if the PMODE[2:0] pins are hard-wired and are independent of FPGA.

Best regards,
Srinath S

[agba_3844561]

Indeed I checked the datasheet. I checked what PMODE is and I concluded it was safe to delete it in my design as I won' t be needing them. I therefore just removed the pins from the FMC Interconnect device and now is working perfectly.

Thank you,