Jan 18, 2019
04:30 AM
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Jan 18, 2019
04:30 AM
I am using a shift register to send out a bit stream (about 2000 bits at 3.3MHZ) which has very tight timing requirements.
The code to write to the shift register is executed inside a critical section.
Without CapSense, everything works fine.
With CapSense, timing problems arise. I was supposing that the interrupt of the CapSense leads to these problems, but other means to disable interrupts like CyGlobalIntDisable have no effect either. I am running out of ideas to solve this problem. Any ideas?
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PSoC 4 Architecture
2 Replies
Jan 18, 2019
04:50 AM
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Jan 18, 2019
04:50 AM
A sample project would help us to debug your issue. Is it possible for you to share a sample project focusing on the issue?
Regards,
Bragadeesh
Regards,
Bragadeesh
Bragadeesh
Feb 06, 2019
05:22 AM
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Feb 06, 2019
05:22 AM
This thread has been locked due to inactivity for more than 3 weeks.
-Cypress Semiconductor
Regards,
Bragadeesh
Bragadeesh