[Verilog] Register access using CY_SET_REG

[TaDa_1407706]

When using PSoC5 verilog component, I can access 8 bit register's data by using below command.

[C code]

        CY_SET_REG8( ComponentName_dataReg0__CONTROL_REG,  0xXX );

[Verilog code]

     wire [7:0] data0;

     cy_psoc3_control #(.cy_init_value (8'h00), .cy_force_order(`TRUE)) dataReg0(.control(data0));

=====

And my question is... "is it possible to get 24/32 bit register's data using CY_SET_REG24/32"???

I think command "cy_psoc3_control" can only apply 8 bit data length.

So could you tell us how to get 32 bit length register's data using verilog code.

[C code]

        CY_SET_REG32( ComponentName_dataReg0__CONTROL_REG,  0xXXXX );

[Verilog code]

     wire [31:0] data0;

     cy_psoc5_control??????

Thank you in advance.

[odissey1 · Accepted solution]

yuusuke.all,

There is only a 8-bit register in PSoC, no 16-32-bit registers. Several 8-bit registers must be combined to make 16, 24 or 32-bit. As an example, please take a look on DDS24 component

DDS24: 24-bit DDS arbitrary frequency generator component

Attached below is example of 8,16,24,32-bit Control and Status register instantiation in Verilog and API read / write access example.

/odissey1

[TaDa_1407706]

Thanks!!!

That's exactly what I want.

I also think that "32-bit parallel non-contiguous GPIO write technique " would be one of the solution.