FM25CL64B to FM25V01A (from 64Kbit SPI FRAM to 128Kbit SPI FRAM)

[AlPa_3955366]

I've been successfully using FM25CL64B (64Kbit SPI FRAM) in tests and in an application. I decided to increase the amount of FRAM and got a couple of FM25V01A's (128Kbit SPI FRAM) to try out. As far as I can tell from the datasheets, there is essentially no difference between the 64 and 128Kbit versions. That is, the pinouts are the same, the op codes are the same. The FM25V01A of course uses one more bit in addressing, but since addresses are two bytes long (with appropriate high bits ignored), there is no difference in SPI data sent via MOSI.

I believe there are some differences in power up time, but those are very little and I've accounted for them as far as I can tell.

There are differences in that the FM25V01A can have various blocks of memory write-protected, but they should come up without protection by default, and I have certainly not changed the register that controls that in any way.

However, my code, which I believe should work essentially seamlessly with the FM25V01A as it does with the FM25CL64B, does not.

I suppose I can't tell if I'm only unable to read OR unable to both write and read (since I can't read ....). With a logic analyzer I can see the clock and MOSI being sent fine. Nothing seems to come down the MISO line.

I've tried two individual chips (thinking that perhaps I'd burnt out the first while soldering the SOIC-8 package to a breakout board), but no. I have two chips not working in precisely the same way.

And so, my questions. Has anyone else had a similar experience moving from the FM25CL64B to the FM25V01A?

Any suggestions?

Thanks for any help.

[PradiptaB_11]

Hi Alan,

To check if the communication is is setup correctly or not can you try reading the device ID for the 128 Kbit device. If you are able to retrieve the ID the device is not burned out.

Also can you read the value of the status register next and let us know. We can know the status of the block protection bits from this and check if any area of the memory is protected.

Also can you please ensure that all the timing requirements according to the 128 Kbit device is met. Like the tVR and tVF spec for the device is 50 and 100 us/V. Kindly ensure this. Also can you check if you are following the AC Switching Char Specs for the device according to the VDD applied to the device.

Thanks,

Pradipta.

[AlPa_3955366]

Pradipta,

Thank you very much for your response.

I have tried the following in my code. In order....

- Wait 100 ms after powering up before initializing the MCU's SPI.

- Set CS high (deselect), wait 10 ms, set CS low (select), wait 10 ms, set CS high, wait 10 ms.

- Attempt to read the chip id with the following code, which has further 10 ms (I've tried longer too) delays that should be ample for the CS ramp up and ramp down times.

void readFramChipIdRegister( FRAM * f, uint8_t * bufferToRead){

  HAL_GPIO_WritePin(f->FRAM_SPI_CS_PIN_BLOCK, f->FRAM_SPI_PIN_NUMBER, GPIO_PIN_RESET);         // Set chip select low; active

  HAL_Delay(10);

  HAL_SPI_Transmit (f->HSPI, &READ_FRAM_CHIP_ID_REGISTER, 1, 10);

  HAL_SPI_Receive (f->HSPI, bufferToRead, sizeof(bufferToRead), 10);

  HAL_GPIO_WritePin(f->FRAM_SPI_CS_PIN_BLOCK, f->FRAM_SPI_PIN_NUMBER, GPIO_PIN_SET);         // Set chip select high; inactive

  HAL_Delay(10);

}

... where READ_FRAM_CHIP_ID_REGISTER is the op code for reading the register

And yet, with my logic analyzer, I see CLK, CS, MOSI all with activity that is correct. MISO has nothing on it.

I believe all my connections are correct because the 64Kbit version of the chip works fine.

Alan

[PradiptaB_11]

Hi Alan,

Can you share with us the power up wave forms and also read ID or status register read wave forms.

Please check if SO is driven by device or not by connecting pull-up on SO pin.

Also can you add a capacitor on VDD line to reduce ramp rate and check if you are able to read device ID or status register.

Thanks,

Pradipta.