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4.1 update one compiles fine, but upgrading to 4.2 breaks the build.
The complaint about preventing usage of special purposes is strange, since those special purposes are not being used.
cydsfit.exe -.appdatapath "C:\Users\fdever\AppData\Local\Cypress Semiconductor\PSoC Creator\4.2" -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\Test_Dual_Valve.cyprj -d CYBLE-214015-01 -s C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\Generated_Source\PSoC4 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
Elaborating Design...
ADD: sdb.M0065: information: Analog terminal "ADC_1M.analog_0" on TopDesign is unconnected.
* C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\TopDesign\TopDesign.cysch (Signal: Net_243)
* C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\TopDesign\TopDesign.cysch (Shape_1872.1)
* C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\TopDesign\TopDesign.cysch (Shape_465)
* C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\TopDesign\TopDesign.cysch (Shape_471)
* C:\Users\fdever\dual_array\firmware\proj\Test_Dual_Valve.cydsn\TopDesign\TopDesign.cysch (Shape_472)
HDL Generation...
Synthesis...
Tech Mapping...
Info: plm.M0038: The pin named \SDI:PIN_SDI12(0)\ at location P3[3] prevents usage of special purposes: SCB[0].uart_cts. (App=cydsfit)
Info: plm.M0038: The pin named \SDI:PIN_SDI12(0)\ at location P3[3] prevents usage of special purposes: SARMUX[0].pads[3]. (App=cydsfit)
Analog Placement...
Analog Routing...
Error: apr.M0003: Unable to find a solution for the analog routing. (App=cydsfit)
Dependency Generation...
Cleanup...
Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)
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Is it possible you upload your project, it is hard to analysis the issue with only the error message. You can remove all codes in project, only leave the schematic which can reproduce the issue.
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This apps note could be helpful to debug this issue.
http://www.cypress.com/documentation/application-notes/an88619-psoc-4-hardware-design-considerations