partial flags of FX3

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MaXi_1246331
Level 4
Level 4
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My application is modified from cypress slave fifo example.

I set one partial flag in GPIF designer. Polarity is active low. Init value is low. The partial flag is for thread 0. thread 0 corresponds to an out endpoint.

In the firmware. My code is CyU3PGpifSocketConfigure(0, CY_U3P_PIB_SOCKET_0,4, CyFalse,1).

Does this If the endpoints contain less than or equal to 4 32bit word. The partial flag should be asserted low?

At power up, the partial flag is high. But the endpoint is surely empty at the start.The partial flag should be low. Then I use control center to tranfer one 32bit word to this endpont. It immediately becomes low. Even When I transfer 1024 byte to this endpoint, it still be low.

This is not what I think of partial flag. Can you explain it? Thank you.

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Hello,

It looks similar what you observed in your case and documented.

Can you please let us know how did you come to this point - "The only difference is my test shows the partial flag get right after the host sent data to FX3, not the master read data from FX3 as described in the doc".

The flags behaves same irrespective of master reading the data or Host sent the data to FX3 (USB -> GPIF).

Above attached document confusion created in Flag status( asserted and deasserted) ,we did flag status corrections please see the attached document.

Was the content of this document true?

The content of document is true.

Does the described problem still exist for newly produced FX3?

Yes, problem still exist.

Regards,

Anil Srinivas.

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alamandaa_16
Moderator
Moderator
Moderator
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Hi,

Please refer to section 8 of  AN65974 for details on using the partial flag.

Regards,

Anil Srinivas.

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I have read the docs and run AN65974, but the described phynominon can not be explained by myself. Would you please explain whether it is the expected result?

Thank you.

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Hi,

Please share the modified GPIF-State machine and firmware.

Regards,

Anil Srinivas.

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Thank you, please see the original firmware of AN65974, I download SF_loopback.img to FX3. I find the inital value of Flag C is low level. This can be understood because at first the FX3 endpoints are empty. Flag C is low active which means it is a no empty flag. low level means it is empty. Please confirn the above understand is correct or not.

However the inital value of Flag D can not be understood. It is high level after initialization. Flag D is partial flag. According to the firmware, If it contains less than or equal to 6 32-bits words, the flag should be asserted. Flag D is low active. The endpoint is empty at start. So flag D should be asserted low. But we see it is a high.

Thank you for your explanation.

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Now I return to my application, if the partial flag are used, the ready flag can be removed?

It seems to me, the partial flag does not respond to clear operation.

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Sorry, I failed to upload the projects. Please see my recent questions on partial flags. Does bug exist in partial flag of out endpoint of FX3?

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Hello,

It looks similar what you observed in your case and documented.

Can you please let us know how did you come to this point - "The only difference is my test shows the partial flag get right after the host sent data to FX3, not the master read data from FX3 as described in the doc".

The flags behaves same irrespective of master reading the data or Host sent the data to FX3 (USB -> GPIF).

Above attached document confusion created in Flag status( asserted and deasserted) ,we did flag status corrections please see the attached document.

Was the content of this document true?

The content of document is true.

Does the described problem still exist for newly produced FX3?

Yes, problem still exist.

Regards,

Anil Srinivas.

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MaXi_1246331
Level 4
Level 4
50 replies posted 25 replies posted 10 replies posted

Can I send the firmware to your email? I do not see the attachment upload button.

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MaXi_1246331
Level 4
Level 4
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This the firmware and GPIF project.

Thank you

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