1 Reply Latest reply on Dec 20, 2018 10:55 PM by zana_2881746

    About read cycle of CE and OE of SRAM CY7C1061G/GE




      Customer refer to the SRAM read control by "Figure 15. Read Cycle No. 3" in the datasheet on page 12.

      In this access, is it possible to read data correctly from SRAM even when "OE goes to Low before CE goes to Low"?

      MCU will act the OE signal to Low about 20ns faster than CS signal to Low in worst case.


      MPN : CY7C1061G/GE



      Best Regards,

      Naoaki Morimoto