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Hi,
I use PSOC creator to design schematic, I want to check correction for the logic sequence of node, is there any tool like logic simulator that could show the logic level diagram?
Chris
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Unfortunately we don't have such tool. However, you could design whatever logic you have in your schematic in Verilog (rather than the graphical tool provided by PSoC Creator). When dealing with Verilog, you can use whatever tool to simulate hardware design, like ModelSim.
Cypress provide the simulation modules for each of the blocks available in the UDBs, like the datapath, status register, control register and the 7-bit counter. They are located at:
C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\sim\presynth\vlg
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Unfortunately we don't have such tool. However, you could design whatever logic you have in your schematic in Verilog (rather than the graphical tool provided by PSoC Creator). When dealing with Verilog, you can use whatever tool to simulate hardware design, like ModelSim.
Cypress provide the simulation modules for each of the blocks available in the UDBs, like the datapath, status register, control register and the 7-bit counter. They are located at:
C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\sim\presynth\vlg
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rlos,
Thanks, I will try to learn hardware language to do this task.
Chris