GPIF Flag setting

[ThM_3776866]

Hai all,

I am working on cypress fx3. I need to interface cypress with external peripherals through GPIF. I need to send data from PC to external device through GPIF 16 bit interface. The GPIF designer as fallow.

Clock = internal.

data width=16.

DMA Flag(GPIO_18)= Thread_0 DMA Ready ( this is the data valid pin to External device)

When Flag_0 asserted external device start to read the data from GPIF port.

GPIO_20(READ)= Used to check external FIFO is free.

Note: The assertion of Flag_0(GPIO_18) is one clock is early and de assertion is one clock late. In this condition external FIFO take 2 sample Extra data (junks data) in every DMA transfer.

1.Why the DAM Flag takes extra 2 clock cycle in every DMA Transfer ?.

2.How to solve this problem?.

3.Is any idea for assertion of valid signal when data is in DMA buffer without considering DMA flag?.

Thank you.

With Best Regards,

Thrimurthi M

[SrinathS_16]

Hello Thrimurthi,

The FX3 flags require 2 clock cycles to assert/de-assert the flag after the DMA is ready to receive/transfer data. To avoid this problem, you can use the DMA watermark flag along with the DMA_Thread0_Ready flag to identify the exact completion of transfer.

Please refer to AN65974 for details on using the DMA Watermark flag.

Best regards,

Srinath S

[ThM_3776866]

Hello sir,

I d'not know how to set watermark value in "CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET_0, 4 ,CyFalse,1).

uint16_t           watermark,           /**< Watermark level for this socket in number of 4-byte words. */

1.What is the meaning of 4-byte word.? if I give 4 as watermark at what clock period Flag will assert?.

2.The polarity of flag is changing when I give active low it assert at active high. how to give polarity of Flag signal?

Thank you

With Best Regards,

Thrimurthi.M

[SrinathS_16 · Accepted solution]

Hello Thrimurthi,

I assume that you are using the FX3 as the slave and the external device as the master. Please correct me if I am wrong.

- When the watermark is set to 4 on a 16-bit bus width slave FIFO interface, the number of clock cycles the SLRD# can be left asserted is given by the below formula as '5'. Please refer to section 8.3 of the AN65974 application note.

          watermark x (32/bus width) – 3

- Double click on the FLAG name in the GPIF II designer and you can change the polarity of the flag.

Best regards,

Srinath S