Slave FIFO Read Sequence in Fx3

[ThM_3776866]

Hi All,

I'm working on Fx3 cypress GPIF Interface. I need to send the data from host to external device through a GPIF interface. I am using DMA_Ready_Flag for Data valid signal to External device and Read signal is from External device to cypress.

The timing diagram of Slave FIFO Read is given bellow.

Q1 why data is sampled after 2nd clock cycle of Flag and read signal is assert?.

Please do the needful.

Thank you

With Beast Regards,

Thrimurthi M

[abhinavg_21]

Hi Thrimurthi,

Please don't rely on the GPIF timing diagrams. Kindly probe the actual physical lines and observe timing diagrams on the SCOPE.

Thanks & RegardsAbhinav

[ThM_3776866]

Yes sir, I probe the Data and Flag signal in CRO, I got same behavior. I shown in bellow figure.

Blue signal: data

Yellow signal: Flag Ready.

In Figure shown the Flag is asserted before 2 clock cycle of data transfer.

[abhinavg_21 · Accepted solution]

Hi,

Please share the system block diagram with all the interface signals clearly mention there working. Also if possible share the project.

Thanks & Regards
Abhinav