I have been racking my brain on how to properly utilize the timer component without wasting time in an ISR (outside of my standard housekeeping routines). I have been experimenting in two separate applications with this timer component, but it seems to be missing some of the standard functions I am used to on other ARM processors (which is likely due to my ignorance).
In the first application, I am reading a tachometer to measure speed via a 24-bit clock timer. Right now the timer is configured to reload automatically on TC, but I have had no way of reloading the timer autonomously when a capture event occurs (i.e. Capture event mirrors TC event to move on and time next pulse while storing current value for read in frame machine/standard housekeeping ISR). To get around this, I am generating a separate ISR "on capture" event and reading the capture within the ISR. This seems clunky, since I am used to seeing reloads on capture and housekeeping by reading status flags and capture values without a separate ISR on other ARMS/TI procs.
I played around with running the "Capture" Hardware bit through two flip flops back into the "Reset" port of the timer as I had seen on adjacent threads, but in testing that appears to clear my status flags and the capture register. It may be important to note that I have relied on testing to verify some of this functionality since some of the finer details related to reset and register status are not defined in the Timer datasheet or the TRM via sections 184.108.40.206 and 220.127.116.11. My assumptions from the TRM are that the UDB hardware reset should only reload the counter value and leave status/capture registers alone (At least in this case it would be ideal).
Random things to mention: I was originally running this block at 32MHz, 32-bit, but ended up slowing things down and decreasing the field-width since the Timer datasheet mentions possible timing concerns at that range.
Circling back, my main question is.. Is it possible to run the timer block to reload autonomously on capture without clearing status bits. Is there a datasheet or TRM that defines this exact behavior? I am attaching pictures of an example of 1 of 3 implementations I have played with to help out and I have no problem showing example sources.
In the second application, I am reading a PWM input and the timer/capture block requires a bit of processor time to dynamic process period count and duty cycle, even using the "Pulse Width Mode" and "Period Mode" defined on 218 and 219 of the TRM for the PSoC 5LP (Document No. 001-69820 Rev. *D, 001-78426 Rev. *F). Is there a way to do this autonomously so that all I am doing is reading captured values from two separate timers in my primary housekeeping ISR? I assume if I am missing something in the first question, this will be answered there.
Thank you for the time,