fx2lp slavefifo

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gean_3054931
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Hello,

I have interfaced fx2lp with image sensor in slavefifo configuration.

in AN61345 ,they have given that "The interface clock (IFCLK) coming from the FPGA is shifted by 180 degrees to meet the setup time requirements of the Slave FIFO interface of FX2LP"

I dint understand the above statement.can you please explain?

and i am facing some timimg issues in my appliation?is it above statement maaters when i am using sensor instead of fpga?

regards,

geetha.

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Sananya_14
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Hello Geetha,

When writing to the slave FIFO interface using the external IFCLK, the setup and hold times must be satisfied by the master as per Table 24 in the datasheet. By inverting the IFCLK, we can ensure a long enough setup time from the FPGA side by delaying the rising edge. For your image sensor, you will be using burst mode to write data hence the timing diagram should match that of Figure 32 from the datasheet for SLWR and data.

Kindly explain what timing issues you are facing?

Best Regards,

Sananya

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Sananya_14
Moderator
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750 replies posted 500 replies posted 250 solutions authored

Hello Geetha,

When writing to the slave FIFO interface using the external IFCLK, the setup and hold times must be satisfied by the master as per Table 24 in the datasheet. By inverting the IFCLK, we can ensure a long enough setup time from the FPGA side by delaying the rising edge. For your image sensor, you will be using burst mode to write data hence the timing diagram should match that of Figure 32 from the datasheet for SLWR and data.

Kindly explain what timing issues you are facing?

Best Regards,

Sananya

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Hello sananya,

can you please look at this thread fx2lp with image sensor .

I have posted my issue regarding image shifting.

regards,

geetha.

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Hello sananya,

the data setup time(tSD) for image sensor is 14ns(min).

the data hold time(tHD) for image sensor is 14ns(min).

In the datasheet,they have given setup and hold time when IFCLK is 48MHZ.

If IFCLK becomes 27MHZ,SETUP time is 5.69ns and HOLD time is 8.005ns.so minimum setup and hold times are satisfied.

regards,

geetha.

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Hello Geetha,

If the setup and hold times are satisfied, there shouldnt be any incorrect data received on the slave FIFO interface. Kindly check how the firmware is handling the received data and how the host application is processing the same.

Best Regards,

Sananya

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Hello sananya,

If the setup and hold times are satisfied, there shouldnt be any incorrect data received on the slave FIFO interface.

-->what ever data is recieved in the pc is correct data.but image is shifted,pixel values are correct.

Kindly check how the firmware is handling the received data and how the host application is processing the same.

frimware is handling the data with slavefifo configuration.

1.line valid is connected to slwr.

2.when slwr gets asstered ,data is written into endpoint 6.

3.in the control center application,host request 360960 bytes and displays the same data.

this data is image (full frame),but image is shifting.

i couldnot able to solve this problem.

regards,

geetha.

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Hello sananya,

can i get any solution from your side?

regards,

geetha.

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Hello Geetha,

-Please check if the data is getting committed when SLWR is asserted from the image sensor and there is no data loss by putting the FX2LP in Auto mode.

-Please save the data on the host application after receiving a complete frame of 360960 bytes to ensure there is not much delay between the transfers on the host side.

Since the pixel values are correct, there seems to be no issue in the setup and hold times on the slave FIFO interface.

Best Regards,

Sananya

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