I2CMasterReadByte returns 0x80000000

[HeGi_2497906]

In the read of a register of the LIS3DH accelerometer below. I am successful up to the MasterReadByte, it returns 0x80000000, can anyone help me understand what that means?  It is not listed in the errors, and only Bob Marlow talks about how the ReadByte does not return standard I2C error codes, is that true, and if so, why not?

uint32 AccelReadByte(uint8 reg_addr)

{

    volatile uint32 I2C_error = TRANSFER_ERROR;

    I2C_I2CMasterClearStatus();

    I2C_I2CMasterClearWriteBuf();

    I2C_I2CMasterClearReadBuf();

    /* I2C read */

    while(I2C_I2C_MSTR_NO_ERROR != I2C_I2CMasterStatus());

    I2C_error = I2C_I2CMasterSendStart(LIS3DH_addr_write,I2C_I2C_WRITE_XFER_MODE,1);

//    while(I2C_I2C_MSTR_NO_ERROR != I2C_I2CMasterStatus());

    if(I2C_error != I2C_I2C_MSTR_NO_ERROR)

    {

        Status = Status | CER;

        I2C_I2CMasterSendRestart(LIS3DH_addr_write,I2C_I2C_WRITE_XFER_MODE,1);

        I2C_error = TRANSFER_ERROR;

        return I2C_error;

    }

    I2C_error = I2C_I2CMasterWriteByte(reg_addr,0);  

    if(I2C_error != I2C_I2C_MSTR_NO_ERROR)

    {

        Status = Status | CER;

        I2C_I2CMasterSendRestart(LIS3DH_addr_write,I2C_I2C_WRITE_XFER_MODE,1);

        I2C_error = TRANSFER_ERROR;

        return I2C_error;

    }

    I2C_error = I2C_I2CMasterSendRestart(LIS3DH_addr_read,I2C_I2C_READ_XFER_MODE,1);  

    if(I2C_error != I2C_I2C_MSTR_NO_ERROR)

    {

        Status = Status | CER;

        I2C_I2CMasterSendRestart(LIS3DH_addr_write,I2C_I2C_WRITE_XFER_MODE,1);

        I2C_error = TRANSFER_ERROR;

        return I2C_error;

    }

    I2C_error = I2C_I2CMasterReadByte(I2C_I2C_NAK_DATA,&I2C_Byte,1);  

//    if(I2C_error != I2C_I2C_MSTR_NO_ERROR)

//    {

//        Status = Status | CER;

//        I2C_I2CMasterSendRestart(LIS3DH_addr_write,I2C_I2C_WRITE_XFER_MODE,0);

//        I2C_error = TRANSFER_ERROR;

//        return I2C_error;

//    }

//   

    I2C_error = I2C_I2CMasterSendStop(1);   // send stop

    if(I2C_error != I2C_I2C_MSTR_NO_ERROR)

    {

        Status = Status | CER;

        I2C_I2CMasterSendRestart(LIS3DH_addr_write,I2C_I2C_WRITE_XFER_MODE,0);

        I2C_error = TRANSFER_ERROR;

        return I2C_error;

    }

    I2C_error = TRANSFER_CMPLT;

    Status = Status & ACER;

    return I2C_error;

}//AccelRead

[Bob_Marlowe]

I cannot see the LIS3DH_addr_write  and _read values, but the component uses 7-bit addresses. The R/W bit is appended automatically.

So the address for reading or writing is the same.

Bob

[HeGi_2497906]

agreed. here are the defines

#define LIS3DH_addr_read         0b0011001 //SA0 high

#define LIS3DH_addr_write        0b0011001

Messing around with bit rates and sampling factors, I have seen the correct response of 0x33, several times now, but it will not work reliably.  Gets hung up on the read.

[HeGi_2497906 · Accepted solution]

Just got the LIS3DH sqwacking back his WhoAMI reg with a value of 0x33!

It was a bunch of small things, I wish I could say what the big issue was, speed settings and such, working for now, will try device config and data collection next