GPIFII Designer project in AN84868 using FX3 to configure FPGA

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MaXi_1246331
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In AN84868, IO matrix configuration are different in configuration phase and slave FIFO transferring phase. The corresponding GPIFII DESIGNER project seems to only match slave fifo io configuration. However, The main firmware project uses 32 bits slave fifo operation and GPIFII DESIGNER project uses 16 bits configuration. Why the two projects do not match with each other? Should GPIFII Designer project have two different configurations corresponding to FPGA configuration and SLAVE FIFO transferring?

Thank you.

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1 Solution
SrinathS_16
Moderator
Moderator
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Hello,

The cyfxgpif2config.h file has been modified to include the check to identify the GPIF II bus width. The below statements identify the IO matrix configuration and modify the GPIF II bus width accordingly at run-time.

#if (CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT == 0)

    0x000010A7,  /*  CY_U3P_PIB_GPIF_BUS_CONFIG */

#else if (CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT ==1)

    0x000010AC, /* 32b data- CY_U3P_PIB_GPIF_BUS_CONFIG */

#endif

Hence, the same .h file can be used for both the configuration of FPGA and the slave FIFO interface.

Best regards,

Srinath S

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2 Replies
SrinathS_16
Moderator
Moderator
Moderator
1000 replies posted 750 replies posted 500 replies posted

Hello,

The cyfxgpif2config.h file has been modified to include the check to identify the GPIF II bus width. The below statements identify the IO matrix configuration and modify the GPIF II bus width accordingly at run-time.

#if (CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT == 0)

    0x000010A7,  /*  CY_U3P_PIB_GPIF_BUS_CONFIG */

#else if (CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT ==1)

    0x000010AC, /* 32b data- CY_U3P_PIB_GPIF_BUS_CONFIG */

#endif

Hence, the same .h file can be used for both the configuration of FPGA and the slave FIFO interface.

Best regards,

Srinath S

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MaXi_1246331
Level 4
Level 4
50 replies posted 25 replies posted 10 replies posted

Thank you. Your answer solves the problem.

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