6 Replies Latest reply on Nov 26, 2018 10:42 PM by prbd

Question about access control of nvSRAM.

morimoto-n_1534561 Nov 18, 2018 9:04 PM

Hello,

Is it possible to execute write access and read access with other control signals (OE, WE) while CE signals (nCE 1, CE 2) are always asserted?

There is no case where CE is always asserted in the AC timing waveform of the data sheet, so it is confirmed.

MPN is CY14B116N-Z45XI.

Best Regards,

Naoaki Morimoto

1. Re: Question about access control of nvSRAM.

prbd Nov 18, 2018 10:40 PM (in response to morimoto-n_1534561)

Hi Naoki-san,

Yes, it is possible.
For a read operation kindly follow read cycle 1 (figure 11) from the datasheet. It is address transition controlled read while CE and OE are both asserted.
For a write operation kindly follow write cycle 1(figure 13) or write cycle 3( figure 15) whichever is more suitable from the datasheet.

Thanks and regards,
Pradipta.
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2. Re: Question about access control of nvSRAM.

morimoto-n_1534561 Nov 21, 2018 10:57 PM (in response to prbd)

Hello Pradipta-san,

Thanks for the reply.
I have additional questions for read access control.
In the previous reply, if CE is de-asserted all the time, valid data will be output after waiting tAA = 45ns (max) after the address changes.
Can I control read access by nWE, nOE signal with CE constantly deasserted?
Or, if there is no rising / falling edge of CE, can not control with nWE, nOE signal?

Best Regards,
Naoaki Morimoto
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3. Re: Question about access control of nvSRAM.

prbd Nov 22, 2018 2:01 AM (in response to morimoto-n_1534561)

Hi Naoki-san,

You cannot control read access by WE# and OE# signals with CE constantly deasserted.

Thanks and Regards,
Pradipta.
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4. Re: Question about access control of nvSRAM.

morimoto-n_1534561 Nov 22, 2018 2:26 AM (in response to prbd)

Hello Pradipta-san,

Sorry, it is a mistype.
The question is under the condition that CE is always asserted.
Can I control read access by nWE, nOE signal while CE is always asserted?

Still the answer is the same as above?

Best Regards,
Naoaki Morimoto
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5. Re: Question about access control of nvSRAM.

morimoto-n_1534561 Nov 26, 2018 8:49 PM (in response to morimoto-n_1534561)

Hello Pradipta-san,

Do you have any update on this?

Best Regards,
Naoaki Morimoto
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6. Re: Question about access control of nvSRAM.

prbd Nov 26, 2018 10:42 PM (in response to morimoto-n_1534561)

Hello Naoki-san,

My apologies for the delay. Yes, the answer remains the same. You need to follow the datasheet wave forms for a read operation to work correctly.

Thanks and Regards,
Pradipta.
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