6 Replies Latest reply on Nov 20, 2018 12:10 AM by YangyangC_06

    IO matrix configuration problems in AN84868

    maxic_1246331
    maxic_1246331 Nov 15, 2018 6:05 AM

      In the code of AN84868 (Configuring an FPGA over USB Using Cypress EZ-USB FX3), the IO matrix configuration in the main function is as follows:

      io_cfg.useUart   = CyTrue;

      io_cfg.useI2C    = CyFalse;

      io_cfg.useI2S    = CyFalse;

      io_cfg.useSpi    = CyTrue;

      io_cfg.isDQ32Bit = CyFalse;

      io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_DEFAULT;

      My first question is CY_U3P_IO_MATRIX_LPP_DEFAULT means to enable all of the low performance peripheral, whereas the I2C, I2S is disabled by  "io_cfg.useI2C    = CyFalse;  io_cfg.useI2S    = CyFalse;".   Is this a contradiction?

      My second question is after running the above code, I mean just complete the above code and before running the following code, will the SPI related IO will still stay float? When does the SPI related IO start to output logic level in AN84868?

      Thank you.

       

       

       

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        • 1. Re: IO matrix configuration problems in AN84868
          YangyangC_06
          YangyangC_06 Moderator Nov 18, 2018 6:24 PM (in response to maxic_1246331)

          Hi Maverick,

           

          For the question 1, well, it seems to  be a "literal contradiction". In fact, I2C interace is always available so that io_cfg.useI2C doesn't make sense. We don't need I2S port in this application so that io_cfg_useI2S= CyFalse.

          However, for FX3, if you configure it to works as 32-bit mode, only one of SPI/UART/I2S is available. In this case, you must set  io.cfg_lppMode to CY_U3P_IO_MATRIX_LPP_DEFAULT. Then set one of io_cfg.useUART/useI2S/useSPI to CyTrue and others CyFalse.

          This is the feature of FX3. It is not totally the same to human intuition but you need to use it in this way.

           

          For question 2, Figure 4 of AN84868 illustrates the procedure. Please refer to it.

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          • 2. Re: IO matrix configuration problems in AN84868
            maxic_1246331
            maxic_1246331 Nov 19, 2018 6:21 AM (in response to YangyangC_06)

            Thank you.

            The first question is nicely solved. However I still have not got the answer for the second question. I think I should state the second question more clearly: When do the SCK pin and MOSI pin of SPI interface leave the tri-state and start to output signals in AN84868.

            Does it happen when I just finish IO matrix configuration by the function of CyU3PDeviceConfigureIOMatrix?

            Or does it happen when I just finish the initialization of SPI interface by the function of CyU3PSpiInit?

            Or does it happen when I just finish the configuration of SPI interface by the function of CyU3PSpiSetConfig?

            • 3. Re: IO matrix configuration problems in AN84868
              YangyangC_06
              YangyangC_06 Moderator Nov 19, 2018 8:58 PM (in response to maxic_1246331)

              Hi Maverick,

               

              The configuration will not happen untill the host send vendor command to FX3. We define vendor command 0xB1 and 0xB2 for implement this. The firmware sets the  event  CY_FX_CONFIGFPGAAPP_START_EVENT  for  starting  the  FPGA  configuration  after  it  receives  the

              vendor command 0xB2  (VND_CMD_SLAVESER_CFGLOAD)  along with the length of the configuration bit file. The firmware  also  sets  the  event  CY_FX_CONFIGFPGAAPP_SW_TO_SLFIFO_EVENT  for  switching  to  the  Slave FIFO  interface  after  it  receives  the  vendor  command  0xB1  (VND_CMD_SLAVESER_CFGSTAT)  and  only  if  the FPGA configuration is successful. After CY_FX_CONFIGFPGAAPP_SW_TO_SLFIFO_EVENT  is set, the firmware will switch to slave FIFO and the I/O matrix will be reconfigured if necessary.

              Section 3.3 and 3.4 makes a very detailed explanation on this part.

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              • 4. Re: IO matrix configuration problems in AN84868
                YangyangC_06
                YangyangC_06 Moderator Nov 19, 2018 9:01 PM (in response to maxic_1246331)

                So the answer for your question is none of the time you have mentioned.

                • 5. Re: IO matrix configuration problems in AN84868
                  maxic_1246331
                  maxic_1246331 Nov 20, 2018 12:01 AM (in response to YangyangC_06)

                  Thank you.

                  Although I understand when will the FX3 start configuration, I still do not know when the spi interface start to leave the float state in this application note. Does SPI interface begin to leave the float state once FX3 receives the configuration command?