Set DMA watermark of FX3

[jach_1279971]

16 bit data bus is used, I set the watermark value to 3, number of 16-bit data words that may be written after the clock edge at which the partial flag is

sampled asserted = 3 x (32/16) – 4 = 2

CyU3PGpifSocketConfigure(0, CY_U3P_PIB_SOCKET_0, 3, CyFalse, 1);

I also set only 1 DMA buffer with 8 bytes depth.

#define CY_FX_DMA_BUF_COUNT      (1)                       /* slave Bulk channel buffer count */

#define CY_FX_DMA_TX_SIZE        (8)                       /* DMA transfer size is set to infinite */

Then I use Control center to write 12 bytes data from master FX3 to slave FX3, it's correct that only 8 bytes can be received by slave. I expect Thread_0_DMA_Watermark (GPIO21) should be deasserted after 6 bytes data is transmitted by master but this pin's value isn't changed. Please kindly advise.

[jach_1279971]

Auto DMA is used, any idea? Thanks.

[Hemanth]

Hi,

As a first step,

Can you make the macro CY_FX_DMA_TX_SIZE as 0 and send 12 bytes?

I have did the same and observed that the watermark flag is driven low. Please confirm this.

Regarding when the watermark flag is asserted:

If you set watermark value to 3, then you are aware that after the watermark flag is asserted, 2 '16 bit words' (which is 4 bytes) can be read out from the current buffer. That means that if you send 12 bytes, the watermark flag should be asserted after sending out 8 bytes.

Regards,

Hemanth

[jach_1279971]

Hi Hemanth,

The initial value of watermark in GPIF II is configured to high with active low trigger. After I set the macro CY_FX_DMA_TX_SIZE as 0 and master send 12 bytes, the watermark GPIO is still always high. Please kindly advise.

[Hemanth]

Can you please try with the attached firmware?

Password: cypress

Regards,

Hemanth

[jach_1279971]

Could you figure out my problem? Thanks.

[jach_1279971]

I have conducted 3 tests by modifying the value of CY_FX_DMA_TX_SIZE in slave side. It's quite weird to get 3 different results.

1. #define CY_FX_DMA_TX_SIZE        (0)                       /* DMA transfer size is set to infinite */

According to the comment, it's infinite buffer size. Master sends 2048 bytes to slave.

It seems DMA_ready and DMA_watermark control signal correctly. After zooming in, I can observe that DMA_watermark is pulled high before DMA_ready, SLWR and SLCS. That's what I want.

2. #define CY_FX_DMA_TX_SIZE        (1024)

Master also sends 2048 bytes to slave but buffer size of slave is reduced to 1024. I can observe that DMA_ready and DMA_watermark are no longer to pull up after receiving first batch of data.

3. #define CY_FX_DMA_TX_SIZE        (8)

Master sends 12 bytes to slave but the buffer size of slave is reduced to 8. DMA_ready and DMA_watermark are changed nothing.

Is it a bug of FX3?

[Hemanth · Accepted solution]

Hi,

By changing CY_FX_DMA_TX_SIZE, you are not changing the buffer size of the Slave device. Instead what happens when you set CY_FX_DMA_TX_SIZE to 8 is that DMA channel goes to idle state after 8 bytes are transmitted.

If you want to change the buffer size, you need to change the dmaCfg.size parameter.

And please note that the buffer size of the DMA channel should be a multiple of 16 bytes.

Regards,

Hemanth