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I can bring in a clk on any GPIO and use it as a digital signal clock, but there is a block in the clock wizard called ExtClk and only P0.6 is possible there. Is this a better pin to bring any external clock in on? Is it a direct, low capacitance line to the clock block? I can't find anything in the TRM or datasheet that explains it.
Solved! Go to Solution.
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Why have the ExtClk block with P0.6 as the only choice? Otherwise, it is just another digital signal into the clock tree / mux. There is nothing in the datasheet or TRM to address this.
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Here is a screen shot of the Clock Wizard.
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P0.6 have no special, just designed as an EXT_CLK pin and it can be routed to the main clock network via internal digital routing and mux.
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Why have the ExtClk block with P0.6 as the only choice? Otherwise, it is just another digital signal into the clock tree / mux. There is nothing in the datasheet or TRM to address this.
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The chip is just designed like that, no special reason. Not just PSoC4A-L, other PSOC4 family parts which support EXT_CLK function also only designed one dedicate pin for the clock routing.
The datasheet mention the function of P0.6 in Pinouts tables, described as "srss.ext_clk:0 ", but seems this is not clear to customer. I will report this issue to document apartment to change that.
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I guess that it saves you from having to put a pin on the schematic, add a wire and give it a name. Then selecting that name in the Clock Wizard. You can just the box of the EXT CLK block and put a clock on P0.6.