FPGA(zc702) cannot receive data from fx3 in stream out mode

[Anonymous]

Hi,

In our system, the CYUSB3KIT-003(synchronous slave fifo 2 bit mode) and xilinx zc702 are used.

in stream_in mode(streamin.img), the system worked normally; but in stream_out(streamout.img) mode, FPGA cannot receive the data from FX3 (please see attachted files)

the control signals from fpga : SLCS is low, SLWR is high, SLOE is low, SLRD is low, FLAGC turns low, PKEND is high, A[1:0]=2'b11

but there is no validate data on the data bus ~

why can this happen and how to figure this out?

Thanks so much~

[KandlaguntaR_36]

Please confirm whether you have done BULTOUT transfers and the data is received by GPIF II consumer socket.

This can be checked via debug prints - tune to DMA Manual Channels and set a flag on success of CyU3PDmaChannelCommitBuffer API in the UtoP DMA Callback and print in the infinite for loop.

Note that when there is a data in the buffer (on GPIF II consumer side), the FLAGC will go high. Please confirm.

[Anonymous]

Hi srdr :

attachted files show the test result :

1 ."BULK OUT tranfser completed"

2. FLAGC become high, but still no validate data on data bus

What else should I pay attention to? Thank you very much~

[KandlaguntaR_36]

We should confirm whethe the GPIF II state machine is going to Read State.

Please use CyU3PGpifGetSMState API and print the states of the machine.

Also share the SlaveFIFO firmware along with GPIF state machine for the review.

[Anonymous]

Hi

SMState = 0x2

please see attached file : fpga_in_out.img

Thank you~

[KandlaguntaR_36 · Accepted solution]

The connections that you provided over FX3 and FPGA interface are fine. Hence, GPIF state machine reached READ state (0x02). This is expected.

Why the data is not coming out is the question here?

It might be due to DMA channel creation.

Confirm whether the DMA channel is created between USB endpoint 0x01 to P-Port consumer socket (CY_U3P_PIB_SOCKET_3)?

I hope that you have not changed the action settings in the READ state. It should be as shown below.