For S25FL128S, what's the meaning of tw(WRR Write Time) ?

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xiaowei_li_3787
Level 4
Level 4

Hi

I am using the flash chips of CYPRESS,S25FL128SAGNFI000, but I have 2 questions that i don't understand..

1, I want to configurate the SR1 and CR1, so, I write the WREN, WRR command, but at the 9.10 Embedded Algorithm Performance Tables, it says that the WRR write time is 500ms, what does this means?

Does it mean that after I input the WRR command and set CS# high, I should wait for 500ms so that the value can be write into the chip ?

And I can do another command only after 500ms?

2,  About the control of the chip, Is this any order demand betweent the WRR and BE command ?

(I think I should configurate the SR/CR and then I can input the BE command , Is this right? )

looking forward to your reply~~thanks

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Apurva_S
Moderator
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100 likes received 500 replies posted 250 solutions authored

Hi,

1. Yes. 500ms is the maximum time that WRR command takes to complete execution. Typically, it should take 140ms.

You should wait for 500ms before performing any other operation on the device.

2. There is no specific order that should be followed while sending the WRR command and BE command.

One thing that should be kept in mind while performing Bulk Erase is that all the Block Protection bits of the Status Register should be set to zero. While performing WRR operation, care should be taken that BP bits are not set to one by mistake.

Thanks and Regards,

Apurva   

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Apurva_S
Moderator
Moderator
Moderator
100 likes received 500 replies posted 250 solutions authored

Hi,

1. Yes. 500ms is the maximum time that WRR command takes to complete execution. Typically, it should take 140ms.

You should wait for 500ms before performing any other operation on the device.

2. There is no specific order that should be followed while sending the WRR command and BE command.

One thing that should be kept in mind while performing Bulk Erase is that all the Block Protection bits of the Status Register should be set to zero. While performing WRR operation, care should be taken that BP bits are not set to one by mistake.

Thanks and Regards,

Apurva   

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Hi,

Thank you so much for your reply.

Question 1 is OK , Thanks.

About Question2, I remember that the chip memory array is all '1' when shipped from cypress, so, can I power up the chip and do the program command at the first time?

or that I must do the Bulk erase command before I program the memory array at the first time ?

Thanks.

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Hi,

When shipped, the entire memory array is erased, i.e. all bits are set to 1.

You can directly start programming a new chip.

Thanks and Regards,

Apurva

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Hi,

Thank you so much for your reply.

It really helps a lot..

Could I bother to ask another question ?

About the BE command, the datasheet says that the typ erase time is 33sec, and 165s max.

At the simulation of the BE commands of the flash, what the erast time will be ? Will it be the typ 33s or max 165s?

(Because I am using the modelsim simulation, and the software run about 100ms when the real time is 70s, so If I want to sim the BE command, when the erast time is 165s, I will need the 33hours in the real , it is kind of too long...Or is there any methods that can decrease the erase time in the simulation? )

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Hi,

Sincere apologies for the delay in my response.

Could you please clarify your question a little. Are you saying that a command which typically takes 70sec to execute in real, takes 100ms to simulate? That means time taken by simulation is 700 times less, right?

So, in that case simulation of BE command should typically take 47ms or maximum 235ms.

Best Regards,

Apurva

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Hi,

Thanks for your reply.

Sorry I didn't say clearly about the time.

The datasheet says that the time of BE command is typ 33sec and max 165sec in real.

But about when I am simulating the model, I found that when the model run 100ms, it takes 70s in the real time, which means I need 6.42hours typ and 33hours max in the real time to sim the BE command, which is kind of too long...

So here is the question:

1, about the BE command, when the model is in the simulation, how long is the erase time?  Will it be the typ 33s or max 165s? or some other time between 33-165s?

2, I applied the simulation at the weekend, but I found a thing that kind of wired..

When I writed the BE into the chip(after WREN), and then I write the RDSR1 command ( I  wanted to read the SR1 to check if the BE is done),but the first RDSR1 command has no output, as is red lined in the picture.

But then I writed the RDSR1 again, there comes the SR1 output and then every RDSR1 had a output..

Wouly you tell me that is this normal ?

1105.PNG

Looking forward to your reply~~~

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Hi,

  1. The bulk erase time will be in the range of 33s and will increase with the device wear out, after applying many P/E cycles.
  2. The first RDSR1 is not working because CS# is not being toggled. It is staying HIGH.

Thanks and Regards,

Apurva

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Hi

Thank you so much!~

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