I have a sensor streaming CSI2 at 1.2 Gbps, 120 fps, resolution 240x180, 2 mipi lanes, RAW12 format --> No problem in this case
I have the possibility to double the data of each pixel --> (480x180), keeping the line readout length fixed --> I cannot stream in this case
while I can correctly stream in the same situation with a mipi2usb done in FPGA instead of CX3.
By artificially extending the readout time on the sensor of each line I can stream correctly from CX3.
I want to stream through CX3 without slowing down the readout of the sensor (or at least understand the CX3 limitation)
My understanding of the issue:
I need 6.4 usec to readout 2 lines (in parallel) on the sensor and I need to committ all the data on the mipi bus during this time (before next 2 lines become available)
The time needed for the mipi to committ data is:
480* 2 *12 bits / 1.2 Gbps / 2 lanes = 4.8 usec + (THS + LineBlanking)
[By measurements I have: THS_Prepare = 220ns, THS_Trail=80ns, LineBlanking=460 ns] --> Total mipi time = 6.4 usec
This leaves 460 ns usec of line/horizontal blanking to the CX3 --> Is this enough (see attached image tek00024.png)?
By relaxing the readout time we are virtually increasing horizontal blanking, and everything seem to work again (we need at least 2.6 usec of line blanking to stream)
What we have tried is to use RGB888 format instead of RAW12. In this case it seems we don't have the limitation, meaning we can stream
480 lines without reducing readout.
This is not acceptable since we have to manage externally the RAW12 data unpacking, and does not explain why the native RAW12 is not working.
This also leads me to think that CSI2 PHY layer may not be the problem but maybe how data is managed in the fixed GPIF.
- RAW12 "demosaicing" is introducing overhead
- Some insufficient buffering during data processing in (or before) the GPIF
- More bandwitdth (2.4 Gbps in case of RGB888 instead of 1.2 Gbps in case of RAW12 are "helping" to consume data faster and suffer less by previous point)
What do you think?
Is there a lower hard limit for line blanking in the Mipi receiver?
Here below the mipi configuration:
CyU3PMipicsiCfg_t RAW12_HQvga =
MIPI_LANES, /* uint8_t numDataLanes */
0, /* uint8_t pllPrd */
39, /* uint16_t pllFbd */
CY_U3P_CSI_PLL_FRS_500_1000M, /* CyU3PMipicsiPllClkFrs_t pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_8, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_8, /* CyU3PMipicsiPllClkDiv_t parClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */
tek00024.png 50.9 K