Typo in "WICED Smart Hardware Interfaces" document

[Anonymous]

MMP920732HW-AN101-R - page 8, paragraph 3:

The maximum SCLK speed supported by SPIFFY1 is 12 MHz in all clock modes. This assumes that the IO

supply rail can be guaranteed to be ≤2.4V. When the IO supply is ≤2.4V, then the SPIFFY1 SCLK is limited to

6 MHz operation.

I believe one of those should be ">"

[MichaelF_56 · Accepted solution]

Yes, I believe this to be a typo.

Essentially, if the supply drops below 2.4V, then the operation of SPI_1 (pins shared with I2C, not available on the SIP module) is limited to 6 MHz.

I believe this typo took a while to find since most members here use the SIP module and cannot use SPIFFY1 on it (internal I2C/EEPROM already using),

[Anonymous]

Thanks! I was assuming so, but wanted to report it to you guys.