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I am attempting to configure the S25FL256S as a boot/configuration flash for a Intel Cyclone V FPGA.
The normal flash programmer does not work (Device ID mismatch).
I found the AppNote AN98558 and built the system to match the AppNote.
After programming the SOF file created by Quartus, I get the following from the nios2-flash-programmer program....
$ nios2-flash-programmer --epcs --base=0x120000 --debug -c "USB-Blaster [USB-1]
"
Reading override file "C:/bin/altera/13.1/nios2eds/bin/nios2-flash-override.txt
Reading override file "C:/bin/altera/13.1/nios2eds/bin/nios2-flash-override.txt
"
Using cable "USB-Blaster [USB-1]", device 1, instance 0x00
Resetting and pausing target processor: OK
Processor data bus width is 32 bits
Looking for EPCS registers at address 0x00120000 (with 32bit alignment)
Initial values: 00000000 00000000 6123D6E8 0000000F 00000000 00000000
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00120100 (with 32bit alignment)
Initial values: 00000000 00000000 6123D6E8 0000000F 00000000 00000000
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00120200 (with 32bit alignment)
Initial values: 00000000 00000000 6123D6E8 0000000F 00000000 00000000
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00120300 (with 32bit alignment)
Initial values: 00000000 00000000 6123D6E8 0000000F 00000000 00000000
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00120400 (with 32bit alignment)
Initial values: 00000000 00000000 6123D6E8 0000000F 00000000 00000000
Not here: reserved fields are non-zero
No EPCS registers found: tried looking at addresses
0x00120000, 0x00120100, 0x00120200, 0x00120300 and 0x00120400
Leaving target processor paused
Also, when putting a o-scope on the flash, there is no toggling of the I/O there.
We know that the I/O of the FPGA are connected correctly because on power-on we see the flash respond with the correct RDID value.
Any ideas on how to get this working?
Thanks!
Mike
Solved! Go to Solution.
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Ok.... so it turns out that the JTAG reset request is resetting the PLL. My solution was to write a wrapper around the QSYS module that forced the PLL reset to always be '0'.
With this setup, I can program the flash properly.
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Hi Mike,
Perhaps something was wrong in the project you built. Can you doublecheck to see if you follow each step in the AN98558 closely? For example, did you define the pin connections in your project? You may share your project system content diagram here so we can take a look.
If you have Quartus Prime 17, you may try that too. The newer Quartus has better auto configuration with the EPCS controller. You may be able to do that more easily.
Thanks,
Zhi
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Thank you for looking into this with me.
I"m trying the flash programming routine in both Quartus 17 and Quartus 13.1.
I'll attach the quartus archive from my Q17 project.
The only difference from the AppNote that I can see is I added a PLL because our board only has a 8MHz clock input and QSYS requires the NIOS to have at least a 20MHz clock.
I hope that you find a flaw in the project!
Thanks!
Mike
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Hi Mike,
Thanks for sharing the project. I think you may be missing some pin assignments. Please take a look at the Figure 6 and Figure 7 of the AN. http://www.cypress.com/file/202476/download .
This is the latest AN in case you had an older version.
Thanks,
Zhi
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When I select the flash controller in QSYS, it gives me two radio buttons like this:
If I select either of these options, the flash I/O are automatically attached to the Active Serial (AS) I/O of the FPGA chip.
If I deselect both options, the flash I/O are brought out to the top-level as a "normal signal". However, the pin planner will not allow me to attach a "normal signal" to the dedicated "AS" I/O.
(The QSPI Flash is attached to the dedicated AS I/O on the circuit board.)
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Hi Mike,
Choosing Automatically select should be fine.
I wondered if this is related to EPCQ256 selection you have in the device selection. Can you try EPCS128 instead? We have not worked with flash density higher than 128Mb because the addressing scheme is a little bit different. However, I don't know why the EPCS controller cannot detect the flash with your project. Usually it is quite a straight forward approach.
Thanks,
Zhi
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The Quartus project does not specify the EPCS size. (Actually it is only allowing a range of 0x7FF bytes.)
Are you suggesting to replace the flash device on the circuit board? I don't have any 128 parts.
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No, I am not suggesting replacing the device. Just the device selection from this window.
Also this window on your project does not seem to show the same pins as in the AN.
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I forgot about the device selection window... it is somewhat hidden.
I don't know why those signals are in that Dual-purpose pins window. There are no signals in the design with that name.
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I modified the device to select the EPCS128 and rebuilt the project in quartus. I uploaded the new SOF file and got the exact same results from nios2-flash-programmer
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I guess that is not the issue.
Looking at your QSYS connection, are you sure the clock is connected from your PLL to the NIOS 2? I don't see a solid dot there, do you?
Thanks,
Zhi
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The NIOS clock is connected to the output of the PLL.
You might notice that there is an onchip_memory block now. I added that so that there would be a real address for the reset and exception vectors to point to. This was necessary to attempt to use the GUI version of the nios2 flash programmer: "nios2-flash-programmer-gui".
The GUI gave the same result... no toggling of the SPI bus when attempting to read the flash.
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In that case, are you missing the clock source for the NIOS2?
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The clock source for the NIOS2 is the output of the PLL. The input to the PLL is the clock pin which attached to a clock source on the circuit board.
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Sorry. I misread your text. I am puzzled why it does not work for you.
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Ok.... so it turns out that the JTAG reset request is resetting the PLL. My solution was to write a wrapper around the QSYS module that forced the PLL reset to always be '0'.
With this setup, I can program the flash properly.
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Ok.... so it turns out that the JTAG reset request is resetting the PLL. My solution was to write a wrapper around the QSYS module that forced the PLL reset to always be '0'.
With this setup, I can program the flash properly.
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That is very good to hear. Thank you for sharing the information.
Please let me know how it goes with your project because you are using a 256Mb device. I will be interested in learning how you do the 4-byte addressing scheme for the upper half of the memory.
Thanks,
Zhi
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I am attempting to replace the legacy controller called out in the AppNote with a newer Altera Flash Controller.
This controller has a parameter page like this:
When set to the EPCQ256, the Qsys tool allows me to set an address range that matches the actual Flash size. (The legacy controller only allowed an address of 0x800.)
The newer flash controller also has a separate interface for CSR access. I'm not totally certain how that should hook up to the NIOS for this programmer scenario. I am currently attaching it like this:
So far, the nios2-flash-programmer is not able to find the flash at either 0x2000000 or 0x10000... I'll keep banging on it.
Thanks,
Mike
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Hi Mike,
I am not familiar with the new EPCQ controller. Sorry not being able to help.
Are you using this controller for your end-product design or just for the in-system programming workaround? If it is the latter, I think you may want to stick with the known working solution. You don't need the new controller, right?
Thanks,
Zhi