Running SAR ADC when CPU is running at 80MHz

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JaLe_2074191
Level 3
Level 3
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I'm trying to find a confuguration where I can run the CPU at maximum speed (80MHz on CY8C5888AXI-LP096 in this case) and also using the SAR_SEQ component.

Setting the Master clock to 80MHz (with XTAL) will result in an ADC clock > 18MHz = error

I tried using an 18MHz XTAL (Master clock 80MHz) = "Error in component: ADC_SAR_Seq_1_SAR. Divider of SAR ADC clock must be 2 or greater when source clock frequency is between 15 MHz and 40 MHz.", setting the Master clock to 72MHz solves this error so the error test is porabably some indirect error.

Does anyone have a working clock configuration to acheive this?

Thanks for any comment on this.

Jacob

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1 Solution
Bob_Marlowe
Level 10
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Setting the Master clock to 80MHz (with XTAL) will result in an ADC clock > 18MHz = error

This is due to a too high sampling frequency. With one channel the sampling can be as high as 1MHz, with two channels only 500kHz.

Bob

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Setting the Master clock to 80MHz (with XTAL) will result in an ADC clock > 18MHz = error

This is due to a too high sampling frequency. With one channel the sampling can be as high as 1MHz, with two channels only 500kHz.

Bob

I get it, I can select a lower sampling frequency even if the clock is higher than the maximum input clock to make it lower. A bit strange that this is not adjusted in the SAR_SEQ UI instead. It is confusing when the component always shows what it "would be" if the input clock is 18MHz, and then some recalculated sampling rate.

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JacobLerenius,

Please check threads below re: overclocking ADC_SAR. The idea is to cheat ADC by preventing it from calculating the clock frequency. If clock connected directly, there is API to obtain its frequency, when some other element is introduced in-between, the frequency is not available and the error is not produced

/odissey1

4MS/s ADC on PSoC5

ADC SAR Overclocking Technique

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