S29GL01GT10FHI010 Compactability for Different VIO and VCC supply

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Anonymous
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Hi,

Q1. Do the Parallel NOR Flash S29GL01GT10FHI010 will operate with VIO=2.5V and VCC=3.3V?
Q2. Else does it need to be replaced with S29GL01GT10FHIV10?

Thanks and Regards

DEEPAK V

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1 Solution
SudheeshK
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Hi Deepak,

As you can see under "Ordering Information" in datasheet on page 101 (http://www.cypress.com/file/218336/download​), only the devices with model numbers V1, V2, V3 and V4 have versatile IO feature (VIO support).

For the device S29GL01GT10FHI'01'0 has model number is '01' and it does not support VIO feature. So, you have to use S29GL01GT10FHI'V1'0, it supports VIO feature.

Thanks and Regards,

Sudheesh

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8 Replies
SudheeshK
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250 sign-ins First question asked 750 replies posted

Hi Deepak,

As you can see under "Ordering Information" in datasheet on page 101 (http://www.cypress.com/file/218336/download​), only the devices with model numbers V1, V2, V3 and V4 have versatile IO feature (VIO support).

For the device S29GL01GT10FHI'01'0 has model number is '01' and it does not support VIO feature. So, you have to use S29GL01GT10FHI'V1'0, it supports VIO feature.

Thanks and Regards,

Sudheesh

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Anonymous
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Hi Sudheesh,

Now I am pretty clear with the Part Numbering information. Thank you for the kind support.

I have a few more questions:
Q1. When VCC= 3.3V and Vio=2.5V, Do the RESET# can be driven by a 2.5V logic similar to all other control signals such as WE#, OE#, CE#, WP#, RY/BY#.
OR
Is it also compatible with 3.3Volt VCC as specified in Table 10.1 of absolute maximum rating?

Q2. Is it Okay to proceed with floating RY/BY# when connecting it to KIntex7 FPGA as it is not one of the configuration signal?

Thanks and Regards

DEEPAK V

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SudheeshK
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Hi Deepak,

Please see our comments below.

Q1. When VCC= 3.3V and Vio=2.5V, Do the RESET# can be driven by a 2.5V logic similar to all other control signals such as WE#, OE#, CE#, WP#, RY/BY#.
OR
Is it also compatible with 3.3Volt VCC as specified in Table 10.1 of absolute maximum rating?

ANS1) RESET# can be driven by 2.5V logic as other IOs in your application.

Q2. Is it Okay to proceed with floating RY/BY# when connecting it to KIntex7 FPGA as it is not one of the configuration signal?

ANS2) RY/BY# pin can be used to check the device status while accessing it. Could you please clarify why you need to leave this pin floating?


Thanks and Regards

Sudheesh

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Anonymous
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Hi Sudheesh,

Q2.Continuing...

I have limited GPIO pins remaining in FPGA. Thus I decided to float it as RY/BY# will not be used by FPGA while it reads BOOT-Image (Configuration File) from the FLASH.

But now I have connected it to FPGA by replacing some other less critical signals.

Q3. Do the Address line have any internal Pull-up or Pull-down?
What happens if any of the Address line is accidentally floated? Do the FLASH will treat it as 'Logic Low' OR it will be an 'undefined state'?

Thanks and Regards

DEEPAK V

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SudheeshK
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Hi Deepak,

We do not recommend to float any of the address lines of our device. A floating address line will be having an undefined state, and it will affect the memory access. So, please connect a pull-up or a pull-down resistor to the unused address lines.

Thanks and Regards,

Sudheesh

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Anonymous
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Hi Sudheesh,

Thank you for the kind help in continuing the support.

One final question more...

Do these both Flash memories S29GL01GT11FHIV20 and S29GL01GT10FHI010 will support indirect programming of Flash through 'VIVADO Programmimg Tool' when used along with Kintex-7 FPGA?
I think it will work fine, Kindly verify it?

Thanks and Regards

DEEPAK V

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SudheeshK
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Hi Deepak,

Sorry for the delay.

Please see the list of our chipset partners from the following link: http://www.cypress.com/chipset-partners​. Our device S29GL01GT is supported by Kintex-7 FPGAs.

Thanks and Regards,

Sudheesh

Anonymous
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Hi Sudheesh,

Thanks once again for sharing the knowledge.

Thanks and Regards

DEEPAK V

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