NAND S34ML01G2 stays busy after issuing page read

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Anonymous
Not applicable

Hi,

I am using S34ML01G1 NAND flash memory to store data. I am able to read from the NAND flash from any address only once. That is, when I repeat the same function of reading data from another address, the NAND remains in busy state(verified by reading status register, status ID 5,6 = 0).

The first address issued was: 0x00000000, that is the very first page of the first block.

The second address issued was: 0x00060000, that is the page address = 6.

Here, the data from the first address is read out properly, but when the same function is used for the second time to read out the data, the NAND remains busy.

Note: this happens in any address issued for the second time.

What am I doing wrong here? Is there any other command that has to be issued apart from 0x30h?

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11 Replies
BushraH_91
Moderator
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750 replies posted 50 likes received 250 solutions authored

Hello,

Thank you for contacting Cypress Community Forum. Can you please do this sequence and provide us all the answers below

  1. Read Status Register
    1. What is the value?
  2. Read Page 0
    1. What is the exact sequence of commands, including details of address cycles?
  3. Read Status Register
    1. What is the value?

Regards,

Bushra

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Anonymous
Not applicable
  1. Read Status Register
    1. What is the value? - 0x60
  2. Read Page 0
    1. What is the exact sequence of commands, including details of address cycles?
      1. Send command 00h
      2. Send Address:
          1. Column address1
          2. Column address2
          3. Page address
          4. Block address
      3. Send command 30h
      4. Check for busy state(by reading status register bit 6)
      5. Send command 00h again(as per datasheet)
      6. Toggle RE pin to read out 2112 bytes
      7. Check for busy state(by reading status register bit 6)
      8. End
  3. Read Status Register
    1. What is the value? - 0x60
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Anonymous
Not applicable

The same status register shows 0x00 while reading page at a different address using the same function, for the second time, which follows the above sequence.

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Anonymous
Not applicable

I have send the sequence and answer to your question.

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BushraH_91
Moderator
Moderator
Moderator
750 replies posted 50 likes received 250 solutions authored

Hello,

Can you please try to send 5 address cycles and test again?

  1. Send Address:
    1. Column address1
    2. Column address2
    3. Page address
    4. Block address
  2. Send command 30h

Thank you

Regards,

Bushra

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Anonymous
Not applicable

Which five address cycles? S34ML01G2 has only four address cycles.However, if you are talking about the sequence, i have already issued 30h after sending the four address cycles.

Sequence:

  1. 00h
  2. Column address
  3. Column address
  4. Page address
  5. Block address
  6. 30h
  7. 70h             // To read status register(bit 6) to check busy status the NAND
  8. 00h
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BushraH_91
Moderator
Moderator
Moderator
750 replies posted 50 likes received 250 solutions authored

Hello,

I am consulting NAND group regarding your issue and will get back to you as soon as I receive their response. Please bear with me.

Thank you

Regards,

Bushra

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Hello,

The 5th address cycle for S34ML01G1 is a dummy address cycle, which will be ignored by the NAND device without causing problems.

Can you please provide your answer for question #1 and question # 2?

  1. Did you check the flash busy status right before the 2nd read operation? Just in case something is going on without awareness.
  2. Please send a reset command (FFh) before the 2nd read sequence, to see what’s going on

Thank you

Regards,

Bushra

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Hello,

We are waiting for your response.

Thank you

Regards,

Bushra

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Hello,

Is your issue resolved? We haven't heard your response for our question.

"The 5th address cycle for S34ML01G1 is a dummy address cycle, which will be ignored by the NAND device without causing problems.

Can you please provide your answer for question #1 and question # 2?

  1. Did you check the flash busy status right before the 2nd read operation? Just in case something is going on without awareness.
  2. Please send a reset command (FFh) before the 2nd read sequence, to see what’s going on"

Thank you

Regards,

Bushra

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Anonymous
Not applicable

Any input on this regard yet?

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