4 Replies Latest reply on Aug 11, 2018 3:53 AM by RaAl_264636

    status register not reading anything?




      I'm trying to debug a design with several calculations done by hardware on a 5LP. So, to get the point where a calculation goes wrong, I used status registers between the blocks to get the partial results. But only two out of six status registers are reading a value, the others always report a zero value. I checked the report file to figure out if those registers have been optimized out, but it seems that they're really included in the design.


      Any ideas what might go wrong? Is there a setting for the Verilog compiler regarding optimization level, wich might influence the design?



        • 1. Re: status register not reading anything?

          If the status registers were optimized out, the compiler would throw Error message in C code, where register is being read. My guess that either timing is wrong or there is indeed just a zero bus state.

          Attaching a demo project would help.


          • 2. Re: status register not reading anything?

            Hi odissey,


            you're right, the compiler doesn't throw an error message. There's a message that unused parts of the design are optimized out, but from the report file, I can't figure out which parts are affected


            I'll try to prepare a stripped down demo project which focuses on the issue.


            By the way, the design uses two of your components, which you provided a time ago (DDS24 and serial multiplier) - those components are worth a lot, so I want to say thank you for sharing those components.



            • 3. Re: status register not reading anything?



              Is your issue resolved? If yes, please share what went wrong so that it will be helpful for other community users.


              If your issue is not resolved, please share a demo project so that we can understand the issue better.




              • 4. Re: status register not reading anything?

                Hello Bragadeesh,


                currently it seems that the issue is resolved.


                The calculations weren't wrong, but the timings (thanks odissey for pointing me into that direction).


                For the issue with the status register: the component has a clock input. I assumed that this input samples the value on the data lines. However, according to component datasheet, this is only true if the data lines are configured as sticky. Otherwise, the read of the register will reflect the value at the time of reading the register. I don't know why reading of some of the register returned a zero value, from datasheet description I expected at least garbage (asynchronous to the design) values because the design should always return a value.

                So, for all users running into that problem: if you need to sample the value synchronous to a signal, you've to set the register inputs to sticky.


                The other issue with wrong results seemed to be a timing issue from one calculation stage to the next. Inverting the clocks of some components solved this issue. Note: I don't fully understand what went wrong. Timing issues seem to be hard to find. So, for now, I'll try to optimize the used custom components.

                As soon as I can provide a stripped down example I'll upload it here. @Cypress: maybe you can also provide example projects showing the pitfalls of such situations.