You start the data transfer only after the device is enumerated(detected in the PC) right?
Please let me know what do you mean by "flipping of data". Can you try transferring the data at lower PCLK? (Just to check whether the issue is seen only at 100MHz)
Are you using http://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-interface firmware? If not please use this.
Yes,I start the data transfer after the device is detected in the PC.
"flipping of data" is meaning that the 32bits data change from 0 to 1 (or from 1 to 0)simultaneously at the frequency of 100MHz .
I am using the fireware you mentioned above..
when the 32bits data goes from 0 to 1 (or from 1 to 0) simultaneously at the frequency of 100MHz .even the control signals disabled(eg,slwr_n keeps high,slrd_n keeps high),the PC can not detect the device.When the data keep unchanged,the PC will detect the device again.
I have test the power that used by CYUSB3014 and FPGA,there is no abnormal condition.
And if I lower the frequency from 100MHz to 75Mhz,the circumstance will not appear.
This may be because the GPIF II power domain gets affected with noise, when the GPIF II data switches at higher rate. If the GPIF II power domain (VIO1 , VIO2) is shorted with other VIO supplies and CVDDQ (in the schematic) , then the noise will propagate to those power domains as well. This may cause data transfer / enumeration issues.
You have to isolate CVDDQ from other VIO domains using choke. You may also try using a stable clock oscillator over a crystal.