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Hi,
I am trying to get a functional camera link using an OV2740 and Cypress CX3.
The OV2740 only outputs in RAW8 @ 1080p 30fps.
Therefore i have adjusted the descriptors as following:
-GUID to 'Y800'
-Number of bits per pixel:8
-Changed bit rate to 1920x1080x30x8
-Changed data format to CY_U3P_CSI_DF_RAW8
In the CX3RDKOV5640 i changed the following line in the ApplInit():
-status = CyU3PMipicsiGpifLoad(CY_U3P_MIPICSI_BUS_8, ES_UVC_DATA_BUF_SIZE);
However when I try to stream using AmCap i get the following error:
Solved! Go to Solution.
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I have done folllowing calculations to find out the CSI clock required for your requirement. This clock is provided by the sensor over MIPI interface.
Pixel clock Frequency = (H_Active+ H_Blanking)*(V_Active+V_Blanking)*fps (pixels/sec) = 2160*1120*30 = 72.576 MHz
Bandwidth = Pixel Clock Frequency* 8 bits per pixel = 72.576 MHz * 8 = 580.608 Mbps
Data Rate per Lane = Bandwidth/2 = 290.304 Mbps
MIPI Bit clock frequency = Data Rate per Lane/2 = 145.152 MHz (approximate to 146 MHz)
The configuration I have got with this CSI clock and other values you mentioned above is as follows (attached the MIPI Configuration Project for reference):
CyU3PMipicsiCfg_t null_RAW8_1080P =
{
CY_U3P_CSI_DF_RAW8, /* CyU3PMipicsiDataFormat_t dataFormat */
2, /* uint8_t numDataLanes */
2, /* uint8_t pllPrd */
99, /* uint16_t pllFbd */
CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */
0, /* uint16_t mClkCtl */
CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */
1920, /* uint16_t hResolution */
40 /* uint16_t fifoDelay */
};
You have to set the PHY Delay 9 using CyU3PMipicsiSetPhyTimeDelay API (Refer API_Guide for more details).
This function should not be called while the MIPI-CSI PLL clocks are active. Either call after calling CyU3PMipicsiSetIntfParams() with wakeOnConfigure set to False (before calling CyU3PMipicsiWakeup() ), or call CyU3PMipicsiSleep() before calling this API.
Please check this KBA for hardware guidelines: CX3 Hardware: Frequently Asked Questions - KBA91295 . Refer Question 2. regarding MCLK.
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Rens,
Please check the following:
1. Is Amcap streams RAW8 data format? If Amcap does not streams, atleast you would see the data stream from image sensor to USB through the debug prints
2. Check whether the Descriptors and Probe Control Settings are changed properly?
3. Whether the MIPI configuration is fine (without any errors in the tool)?
Please go through this similar thread: Streaming RAW8 or RAW10 using CX3
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Hi,
Amcap did indeed not stream raw8 format.
I have now setup the guvcview app, with no advance.
Below is the debug sequence of the usb events.
When I stream using guvcview the descriptor settings are shown correctly as being 1920p@30fps, using greyscale as videoformat.
Which tool should I use for the mipi config?
I have started from the OV5640 example and started adapting to what I need, without coming across a tool?
Thanks already for the answers!
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Rens Baeyens,
Please go through this app note: http://www.cypress.com/documentation/application-notes/an90369-how-interface-mipi-csi-2-image-sensor... especially section 5.5 Configuring the MIPI CSI-2 Controller. This talks about the MIPI Configuration tool.
I recommend you to update to SDK 1.3.4 before starting to work on this tool, if you have not updated yet.
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Hi,
I tried using the mipi config tool, however it returns an error when I try to proceed.
I have therefore manually calculated the clock values using excel.
Could you please verify the following settings?
/* Configuration parameters for 1080p @30FPS for the OV2740 sensor */
CyU3PMipicsiCfg_t cfgUvc1080p30NoMclk = {
CY_U3P_CSI_DF_RAW8, /* dataFormat */
2, /* numDataLanes */
1, /* pllPrd */ //TODO check pll
59, /* pllFbd (62) */
CY_U3P_CSI_PLL_FRS_500_1000M, /* pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_8, /* csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_8, /* parClkDiv */
0x11, /* mclkCtl */
CY_U3P_CSI_PLL_CLK_DIV_8, /* mClkRefDiv */
1920, /* hResolution */
0x01 /* fifoDelay */
};
When programming with these settings, the device returns a shaking stream of the image below (clock issue?)
It is an image of a ceiling lamp, which seems to be spread out across the image.
Do you have an idea what could be causing this maybe?
Thanks!
Rens
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Can you please provide the following details to provide the MIPI configuration?
1. CSI Clock
2. Data Lane
3. THS-Prepare
4. THS-Zero
5. Fps
6. H_Active
7. H_Blanking
8. V_Active
9. V_Blanking
10. Input Data Format
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1. CSI Clock: REFCLK = 19.2MHz
2. 2 data lanes
3. THS-prep - 55.56
4. THS-zero - 120.33
5. 30fps
6. 1920
7. 240
8. 1080
9. 40
10. RAW8
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UPDATE -
I made a mistake in my manual calculations for the pll_clk settings. ( previously i thought the refclk to be 24MHz, but that's the camera Input_clk)
The image looks more stable now, but there are still some crooked things in it.
Do you have an idea which parameters I should be looking at right now?
I have appended two images, one being a checkers test pattern, and the other a picture of some scribble in my notebook.
So the problems remaining:
-Image is tilted, starting at 120px from the top right side
-pixels are shifted in a seemingly random way
-image does not fill 1080p
VAL | MAX | MIN | CLK | ||
---|---|---|---|---|---|
PLLCLK | 720 | 1000 | 500 | 720Mhz | PLLCLK = REFCLK * ((PLL_FBD +1)/(PLL_RPD+1))/(2^PLL_FRS) |
REFCLK | 19,2 | 100 | 0 | 19,2Mhz | |
PLL_FBD | 74 | 511 | 0 | ||
PLL_PRD | 1 | 15 | 0 | ||
PLL_FRS | 0 | 3 | 0 | ||
CSIRX_DIV | 8 | 125 | 0 | 90 | |
PCLK | 8 | 100 | 0 | 90 | |
MCLK | 24 | MCLK=(PLL_CLK/mCLKRefDiv)/((HighByte(MClkCtl)+1)+(LowByte(MClkCtl)+1)) | |||
mClkRefDiv | 2 | 8 | 4 | 2 | |
mClkCtl(HB) | 8 | ||||
mClkCtl(LB) | 5 |
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I have done folllowing calculations to find out the CSI clock required for your requirement. This clock is provided by the sensor over MIPI interface.
Pixel clock Frequency = (H_Active+ H_Blanking)*(V_Active+V_Blanking)*fps (pixels/sec) = 2160*1120*30 = 72.576 MHz
Bandwidth = Pixel Clock Frequency* 8 bits per pixel = 72.576 MHz * 8 = 580.608 Mbps
Data Rate per Lane = Bandwidth/2 = 290.304 Mbps
MIPI Bit clock frequency = Data Rate per Lane/2 = 145.152 MHz (approximate to 146 MHz)
The configuration I have got with this CSI clock and other values you mentioned above is as follows (attached the MIPI Configuration Project for reference):
CyU3PMipicsiCfg_t null_RAW8_1080P =
{
CY_U3P_CSI_DF_RAW8, /* CyU3PMipicsiDataFormat_t dataFormat */
2, /* uint8_t numDataLanes */
2, /* uint8_t pllPrd */
99, /* uint16_t pllFbd */
CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */
0, /* uint16_t mClkCtl */
CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */
1920, /* uint16_t hResolution */
40 /* uint16_t fifoDelay */
};
You have to set the PHY Delay 9 using CyU3PMipicsiSetPhyTimeDelay API (Refer API_Guide for more details).
This function should not be called while the MIPI-CSI PLL clocks are active. Either call after calling CyU3PMipicsiSetIntfParams() with wakeOnConfigure set to False (before calling CyU3PMipicsiWakeup() ), or call CyU3PMipicsiSleep() before calling this API.
Please check this KBA for hardware guidelines: CX3 Hardware: Frequently Asked Questions - KBA91295 . Refer Question 2. regarding MCLK.
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Hi!
Thanks for the effort!
However, the same problems still remain or increase.
Below a picture of the checkers test pattern when I set it to your recommended values.
Problems:
-Right shift per row
-Image stops at approx y=650
Kind regards,
Rens
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Please probe the following test pins and update the values.
G6 - HSYNC_test I/O
H5 - VSYNC_test I/O
H8 - PCLK_test I/O
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Hi!
I have measured and compared my setup using the ov2241 with the functioning denebola rdk using ov5640.
OV5640:
-HSYNC: steady at 2.13V
-VSYNC: steady at 3.3V
-PCLK: Active
OV2241:
-HSYNC: steady at 2.13V
-VSYNC: steady at 3.3V
PCLK: 0V no activity!
What could cause the PCLK to remain unactive?
Thanks!
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I mean H_Active and H_Blank duration. Similarly V_SYNC.
What is the CSI clok frequency that the Sensor is feeding to MIPI of CX3?
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The HSYNC(G6) and VSYNC(H5) lines are stable at the voltage mentioned.
Should the Active and blanking periods be viewable on those lines?
According to the timing sheet from the camera, the following clocks are used on the MIPI line:
-MIPI_CLK: 720Mbps
-MIPI_PCLK: 90MHz
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Hi,
Sorry, I was measuring at the wrong testpins.
Right now, I got a clear signal when measuring.
The PCLK is at 80MHz.
The Vsync is at the correct frame rate (30fps) active period: 32.92ms blanking period: 680us
In the Hsync line, after 11 regular pulses at 20us apart, a larger pulse shows up.
end of bug to start of regular
last regular before bug, first regular after bug
Vsync total
Vsync blanking
Hsync regular pulses
Hsync regular pulse width
Hsync bug pulse width
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This is a picture of the current image coming out of the sensor, it is showing the same image 3 times shifted over the screen, probably due to a mismatch of the hsync?
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Would it be possible to set up a videocall for support?
Since we are quite quickly approaching a deadline, and the progress is
currently too slow to meet the deadline.
Kind regards,
Rens Baeyens
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Hi,
The issues are resolved.
The settings you provided me with were correct!
The remaining issues were on the camera side.
Thanks for your assistance!
Kind regards,
Rens
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Hi Rens,
The AMCap doesnt support custom formats. You need to add support for accessing the custom format on Directshow filter. You need to create a transform filter to do the processing.
Regards,
Shanthakumar
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guvcview application in Ubuntu supports RAW8 format. I can successfully see video streaming with the following GUID settings in descriptor.
/* GUID, globally unique identifier used to identify streaming-encoding format: RAW8 */
'Y', '8', ' ', ' ',
0x00, 0x00, 0x10, 0x00,
0x80, 0x00, 0x00, 0xAA,
0x00, 0x38, 0x9B, 0x71,