How much of "Psoc 4100PS IDAC7" data update ratio?

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
HaLi_1053816
Level 1
Level 1
First like given Welcome!

I have tried it, seem as 3MHZ, is it correct? Thanks.

0 Likes
1 Solution

The DMA channel is triggered by a logic HIGH/1 on the tr_in terminal. The minimum width of this logic HIGH/1 is 2 system clock (SYSCLK) cycles.

Thanks,

Ryan

View solution in original post

0 Likes
3 Replies
RyanZhao
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Dear Mr.Liu,

If the uA or bits value in the Component configuration GUI is set a fixed value, IDAC will keep a stable output.

What do you mean " data update ratio"?

Do you mean if you use Some APIs, like 'IDAC7_SetValue()', to update the output of IDAC7 in run time?

Thanks,

Ryan

0 Likes
HaLi_1053816
Level 1
Level 1
First like given Welcome!

Hello Ryan,

I use DMA drive the IDAC, my mean's DMA transfer data ratio.

Thank a lot.

Haixian

0 Likes

The DMA channel is triggered by a logic HIGH/1 on the tr_in terminal. The minimum width of this logic HIGH/1 is 2 system clock (SYSCLK) cycles.

Thanks,

Ryan

0 Likes