10 Replies Latest reply on Jul 24, 2018 7:01 PM by yzhc_1339276

FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

yzhc_1339276 Jul 23, 2018 7:15 PM

Hello, everyone.

I have related development experience with cyusb3014. In order to quickly integrate FX3 to our system, we used CYUSB3KIT-003. And it worked normally.

About three weeks ago, the CYUSB3KIT-003 was broken. and I bought another board to replace it. but something strange happened.

It couldn't work as expected. But we just used the same FPGA, same Verilog program, same connection with CYUSB3KIT, same fireware image file.

In our system, the synchronous slave fifo mode is used. However, FPGA cannot receive the data from FX3. according to the sampling of the signal line by chipscope,

the control signals are normal, that is, slcs is low, slwr is high, and sloe, slrd is low, flagc turns low. but there is no validate data on the data bus although Control Center has sent data to FX3.

and for the previous broken board, the system just run normally.

why can this happen? how to figure this out? any ideas? Thank you very much.

1. Re: FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

yzhc_1339276 Jul 23, 2018 7:31 PM (in response to yzhc_1339276)

Plus: the broken CYUSB3KIT-003 version is CYUSB3014-BZX I 1437 and the new one is C 1719
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2. Re: FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

SrinathS_16 Jul 23, 2018 8:49 PM (in response to yzhc_1339276)

Hello Zheng,

Please check if the PKEND pin of the FX3 is pulled HIGH. The state machine expects this pin to be HIGH to switch the state so that the data is driven out to FPGA.

Best regards,
Srinath S
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3. Re: FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

yzhc_1339276 Jul 24, 2018 2:36 AM (in response to SrinathS_16)

Hello Srinath S,
First, I want to say thanks to you. I have tried again according to your reminder. it works now. But I still have some questions that i want to talk with you.
In my system, I just use control center on upper computer to send data to FX3, and then FPGA read from FX3. so I choose the streamOUT mode. According to 65974, This PKTEND signal is asserted to write a short packet or a zero-length packet to Slave FIFO. So it will always keep high in streamOUT mode.
Based on this, So we left the PKTEND line unconnected between FX3 and FPGA in the previous board. and in the verilog program, I declare the signal PKTEND always keeps high. The system run normally. FPGA could read from FX3.
For the new CYUSB3KIT-003, it has no response on the databus while the PKTEND line leaves unconnected. But when I keep the PKTEND line connected, FPGA can read from FX3 successfully.
Fortunately, it can work now. but why it could happen? Looking forward to listening to your ideas.

Many thanks,

yz
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4. Re: FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

SrinathS_16 Jul 24, 2018 2:41 AM (in response to yzhc_1339276)

Hello Zheng,

The PKEND pin is a GPIO pin on the FX3.By default, the GPIOs on the FX3 board are floating. So, the PKEND pin may be treated as HIGH or LOW and may cause erroneous results as it happened in your case. To overcome this, you should have to pull the PKEND pin HIGH or modify the state machine to be independent of PKEND pin.

Best regards,
Srinath S
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5. Re: FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

yzhc_1339276 Jul 24, 2018 2:45 AM (in response to yzhc_1339276)

Plus: actually, I have another new CYUSB3KIT-003 board. and for this board, I have the PKTEND line connected between FC3 and PFGA. and I used chipscope to sample the signals. all the control signal and flag signal were normal. and the state machine successfully skip to the read state. But there are no data on the databus. Why?
The situation is getting more and more confused according to above descriptions. ANY IDEAS? Thank you very much.
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6. Re: FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

SrinathS_16 Jul 24, 2018 2:50 AM (in response to yzhc_1339276)

Hello Zheng,

- Can you please check if the Address lines A[1:0] are connected properly?
- In case you still face issues, kindly, capture the UART logs using the on-board USB-Serial chip and share the same.

Best regards,
Srinath S
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7. Re: FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

yzhc_1339276 Jul 24, 2018 3:07 AM (in response to SrinathS_16)

Plus: actually, I have another new CYUSB3KIT-003 board. and for this board, I have the PKTEND line connected between FC3 and PFGA. and I used chipscope to sample the signals. all the control signal and flag signal were normal. and the state machine successfully skip to the read state. But there are no data on the databus. Why?
The situation is getting more and more confused according to above descriptions. ANY IDEAS? Thank you very much.
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8. Re: FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

yzhc_1339276 Jul 24, 2018 3:16 AM (in response to SrinathS_16)

The address line are assigned 11. and they connected properly. Thank you so much, sir.
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9. Re: FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

SrinathS_16 Jul 24, 2018 3:44 AM (in response to yzhc_1339276)

Hello Zheng,

Can you please obtain the UART traces using the on-board USB-Serial device?

Best regards,
Srinath S
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10. Re: FPGA cannot receive data from fx3 in stream out mode in synchronous_ slave_fifo_2bit

yzhc_1339276 Jul 24, 2018 7:01 PM (in response to SrinathS_16)

Thank you very much.
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