- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi, everyone:
I get a problem with FX3 GPIF port.
According to my understanding,a P to U DMA manual Channel will commit data to Host in follow two conditions:
1. one buffer filled
2. PKTEND became low
In my test, I control the PKTEND in FPGA, and the last data packet is not equal to the buffer size , sometime HOST can receive the last packet, but sometime can not, until the buffer size that include the last packet filled with the next fram data packet. I am sure the FPGA prroutine is fine, it seems like the FX3 didn't respond the PKTEND.
Are there any suggestions? Or are there any other way to control the condition that commit data?
Solved! Go to Solution.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Liu Hengliang,
Please check the FIFOADDR Lines. It must be held constant during the PKTEND# assertion.
Regards,
Anil Srinivas.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Liu Hengliang,
Please check the FIFOADDR Lines. It must be held constant during the PKTEND# assertion.
Regards,
Anil Srinivas.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi, aani:
I just have one FX3 as slave FIFO , so i set the A[1:0] as constant value 0 in FPGA. It looks like no problem.
Any other suggestions ?
Please.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
1. Please confirm whether your using the slave fifo example code provided with AN65974?
2.Please attach the slave fifo interface timing diagram.
Regards,
Anil Srinivas.