I'm using an I2C Master component (tried both fixed and UDB) when I2C_1_GENERATE_START_MANUAL is executed, the SCL line goes low and stays there (i.e. there is no clock). This happens for fixed and UDB.

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JaBe_1397886
Level 1
Level 1

I'm using an I2C Master component (tried both fixed and UDB) when I2C_1_GENERATE_START_MANUAL is executed, the SCL line goes low and stays there (i.e. there is no clock). This happens for fixed and UDB.

Execution goes through all of the functions and returns with the clock line stuck at 0,

Any ideas?

  Tnx.

    Jim B.

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1 Solution

When you address a slave at 0x7f the master will send a 0xf7 or 0xff. Last bit is for read and write (0,1).

Make darn sure that your LCD's 7-bit address is 0x7f and not 0x3f. The latter will get 0x7f automatically for a master read.

Bob

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ShanmathiN_06
Employee
Employee
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Hi,

Did you try using code example DelSig_I2CM? If you still face the clock stuck issue in the example project, please provide SCL and SDA scope shots when no slave is connected on the bus.

Else, you can provide your code snippet and I2C component configuration details, along with the scope shots when no slave is connected on the bus.

Thanks,
Shanmathi

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Hi Shanmathi-

That was going to be my next step. Disconnecting the slave is a little difficult (an LCD) because of the construction but I think I can do it.

Will let you know. I am off today so tomorrow is it.

Tnx,

Jim B.

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Shanmathi-

I did a better job setting up the scope in single shot mode.

I now get the start condition (SDA goes low) and 9 clock cycles before the SCL is held at 0. The SDA line is at 1 on the 9th clock pulse. Then everything stops.

I’ll keep at it. If you have any ideas, let me know.

Tnx,

Jim B.

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Hi Jim,

"By then everything stops", do you mean that SCL and SDA are held high at logic '1'?

If that is the case, then that is the expected scenario.

Start condition followed by 9 clock cycles and since there is no slave on the bus, I expect SDA to be high.

So, it looks like the slave was pulling SCL line "low" earlier, after a start condition was detected.

Thanks,
Shanmathi

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Shanmathi-

No, SCL gets held at logic low. What I meant was that all other communication that is supposed to happen with the slave stops because SCL is permanently low.

I am going to do more today and will send you photos of the scope.

Tnx,

Jim B.

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Shanmathi-

The waveform for the address send indicates that the address bits are OK. During the acknowledge clock pulse (9th clock) the SDA line is high (it’s supposed to be LOW correct ?) After the 9th clock, SDA remains high and SCL LOW forever.

This seems to indicate that the slave is not responding, right?

Let me know. I can send you Pix and code if you need.

Tnx.

Jim B.

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Hi Jim,

Yes, please send the code and pics.

Is the slave also connected on the bus? Let me know the exact setup too.

Thanks,
Shanmathi

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Shanmathi-

Ok. I was in the field the last 2 days and not working on it. I will send you stuff later today or tomorrow AM.

I added a pull-up to the clock line (1K) and uses Open drain selection on the pin. The behavior is the same but in detailing the clock edges there may be some extra transitions. I am going to try a series resistor for damping in case that is a problem.

I’ll put a package together and send it along.

Tnx for the support.

* Jim B.

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Shanmathi-

Attached is a pix of the scope with i2C Master sending slave address 0x78. The master is the Psoc and the slave is an LCD display. Note that there is no ACK. Also note that the first address bit sent is 1. Shouldn’t it be 0 ? It looks to me that the Master is sending address 0xf0 instead of 0x7f . The slave is supposed to respond to 0x7f.

What do you think ?

Tnx,

Jim B.

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When you address a slave at 0x7f the master will send a 0xf7 or 0xff. Last bit is for read and write (0,1).

Make darn sure that your LCD's 7-bit address is 0x7f and not 0x3f. The latter will get 0x7f automatically for a master read.

Bob

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Bob-

The slave address is 0x78 . This is what the master is sending. It looks like 0xF0. We can see the START condition but id the address is not right, the slave does not ACK as we see here. Shouldn’t the first data bit of the address (first clock transition high) be 0 for 0x78 ?

Tnx,

Jim B.

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Shouldn’t the first data bit of the address  (first clock transition high) be 0 for 0x78

No, as I tried to say before, the 7-bit address is shifted left and the read/write bit gets appended. So the first bit is a one.

Bob

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Bob-

Aha. Now I know why I am confused. The slave data sheet shows a transaction for an address of 0x78 and the first bit is 0. (See attached) as opposed to what you told me (which makes more sense).

The LCD and LCD controller data sheets say the same thing.

I tried making the address 0x3c. The master did not send 0x3c but some other crazy value.

Maybe I should disconnect the slave just to see what comes out under that condition.

* Jim B,

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I tried making the address 0x3c. The master did not send 0x3c but some other crazy value.

This is experimental data processing. The master will send a 0x79 address when reading.

Bob

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Bob-

I’m going to send you a scope shot of the transaction using 0x3c. According to what you said, this gets shifted left and should come out as 0x78 . Please look at it and comment.

I will do this in a bit. I have to break right now.

* Jim B.

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Bob-

Ok. It’s all working now. I used address 0x3c but did not realize that the LCD slave was receiving the rest of the data correctly until I set multiple breakpoints. Also had to modify some of the setup data.

Apparently the LCD controller’s interpretation of the address phase is different than Cypresses. The data phases are consistent. As long as this is known, it’s OK and we can work with it.

Go ahead and close the case for now.

Tnx for the help.

* Jim B.

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