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Hi everyone,
I'm currently looking into safety-critical related HW options in the PSoC5lp.
NMI seems to be only pendable by software, however the PSoC5lp Registers TRM states that when the NMI_SRCSEL bit of the PANTHER_WAITPIPE register is set to 1, the NMI line is fed with DSI_01_OUT_P_11 signal. What is this signal ? Is it routable through UDB/datapath blocks ?
I also read the "Definitive Guide to the ARM Cortex-M3" book by Joseph Yiu and was wondering how the LOCKUP signal (section 12.5) is used in the PSoC5lp. Does it trigger a SystemReset ?
Regards,
Cédric
Solved! Go to Solution.
- Labels:
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PSoC 5 Architecture
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PSoC 5LP
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- nmi
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PSoC Creator does not expose the NMI directly. And there is no process officially documented/supported by PSoC Creator.
Thanks
Jobin GT
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DSI_01_OUT_P_11 is a DSI location.
The DSI location is encoded with the following information:
1.) The DSI number (00-09, 12, 13)
2.) “in” or “out” signal (all signal directions are described with respect to the UDB array, so an “in” signal is a signal that is entering the UDB array from outside, and an “out” signal is a signal leaving the UDB array)
3.) The connection type “p” or “t” which represents the number of connections on the DSI. A “p” stands for pair, meaning there are two connections on the DSI for the associated signal. A “t” represents a triplet, meaning there are three connections on the DSI for the associated signal.
4.) The connection number (in p # 0 – 24, out p # 0 – 15, out t # 0 – 15)
.dsi_01_out_p_11( cm3_dsi_nmi ), // non-maskable interrupt to the Cortex M3
the NMI interrupt can be triggered by this pin after enabling the NMI_SRCSEL bit
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PSoC Creator does not expose the NMI directly. And there is no process officially documented/supported by PSoC Creator.
Thanks
Jobin GT